SU1619260A1 - Matrix-type squaring device - Google Patents

Abstract

The invention relates to computing and allows the n-bit number to be squared with the control and discrimination of errors in the main and control equipment, which is the aim of the invention. The device contains a matrix of cells of n-1 rows and n / 2 columns consisting of AND elements, adders and calculating 2p bits of the result. The result is written to the output register 10, from which it enters the outputs of the device and through modulo-two adders to the inputs of the convolution unit modulo three. At the outputs of the first adder and the convolution block, a three-digit modulo control code is generated modulo three results, the two values of which 101 and 010 are prohibited. Two modulo-two adders and the And element form on the forbidden values of the control code an error signal, which is received into the trigger and, from its output, inverts the result value on the modulators of two. With the correct operation of the control units, the signal at the input, the trigger is confirmed, which is fixed by the modulo-two adder and is recorded, as well as the signal from the trigger, in the control register, 2 Il.

Description

The invention relates to computing and can be used with specialized computers.

The purpose of the invention is to increase the reliability of the operation. Figure 1 shows the structural diagram of the device for the case in figure 2 - time diagrams of operation.

The device includes elements And 1, adders 2, a group of adders 3.1-3.11 modulo two, block 4 convolution

modulo three, first 5, second 6 and third 7 modulo adders two, element 8, trigger 9, output register 10 and control register 11.

The device works as follows.

The operand enters the inputs of the bits of the operand. In this case, the first bit of the operand is fed to the first information input of the output register 10, the second bit output of the result of the device constantly takes the

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nor logical zero. In addition, the first bit 1p is fed to the first inputs of the And 1 elements of the first column, the second inputs of which receive, respectively, the bits of the operand 2p, 3p, 4p, 5p and 6p. At the outputs of the And 1 elements of the first column, p-2p, p-3p, 1p-4p, 1p.5p, conjunctions are formed, which are fed to the second inputs of the corresponding adders 2 of the first column. Through the first inputs and outputs of these adders 2, as in the adder 2 of the subsequent columns, the transfer signal propagates (except for the first input of the first adder two, which, as in the subsequent columns, is zeroed, as well as the first output of the last fifth adder 2, from the output of which, as in the second column, the transfer signal enters the third input of the fourth adder 2 of the subsequent column, the transfer signal propagates and enters the third input of the fourth adder 2 of the subsequent column). The third inputs of the even adders of the first column are zeroed, and the third inputs of the first, third, and fifth adders 2 of the first column receive bits of the operand, respectively, 2p, 3p, 4p. In this case, the third and fourth bits of the result are determined, coming from the second outputs of the first and second adders 2 of the first column to the second and third information inputs of the output register 10, respectively. The sum signals from the second outputs of the third, fourth, and p one-second adders 2 of the first column are received, as are the sum signals from the corresponding adders 2 of the second column, to the third inputs of the first, second and third sum-1 ditch 2 of the next column, respectively. Elements And 1 of the second column are calculated in accordance with the bits of the operand of the conjunction 2p-3p, 2p.4p, 2p "5p, 2p 6p," entered into their inputs, which are fed to the second inputs of adders 2 of the second column. The third input of the fifth adder 2 of the second column receives the bit of the operand 5p. The fifth and sixth bits of the result are determined from the second outputs of the first and second adders 2 of the second column to the fourth and fifth fifth information inputs of the output register 10, respectively.

0

0

five

0

five

0

Elements And 1 of the third column are determined according to the bits of the operand entered at their inputs.

conjunction Zr 4r, Zr Zr, Zr.br, 4r 6r, Zr br, which are received at the second inputs of the corresponding adders 2 of the third column. To the third input of the second adder 2 of the third

the column goes to the 6p operand bit. The following bits of the result are determined from the second outputs of the adder 2 of the third column and the first output of the fifth totalizer 2 of the third column respectively to the information inputs of the output register 10 from the sixth to the eleventh. The synchronous input of the output register 10 is fed through the clock input of the device type meander. On the falling edge of the SI clock signal, the result bits are received in the output register 10 (FIG. 2), from whose outputs the result

5 to the inputs of the device: the first and from the third to the twelfth, in accordance with the bits of the result - 1рр и.

In addition, the bits of the pp result and go to the first inputs of adders 3.1-3.11 modulo two groups, respectively. The second inputs of the adders 3.1-3.11 group receives a signal from the output of the trigger 9, receiving when the device is working correctly, zero. The same value is the initial state of the trigger 9 for the device operation, which is achieved by putting the original operable device into operation or initial triggers of the trigger 9 and the control register 11 to the zero state after the second SR sync pulse before starting (the reset circuits are not shown for better reception). these devices). The zero value of the signal at the output of the flip-flop 9 ensures the passage of the bits of the Zrr-12pr result without changing through the adders 3.2-Z. And modulo the inputs of the convolution unit 4 modulo two respectively from first to tenth, and also the first bit of the result 1p through the adder 3.1 modulo two groups to the second input of the second adder 6 modulo

$ two. At the same time, modulo two reconciliation unit 4 forms the remainder of dividing the ten most significant bits of the result by module three. Two digits received

5 16

the remainder together with the result bit 1pp (considering that) make up the three-digit control code | Jpp, 2, lJ modulo three of the whole result, and this control code cannot take 101 and 010 values for a correct squaring result. the values are extracted in the control code using the first 5 and second 6 modulo-two adders, which at these values and only at them simultaneously take on the unit and zero values, which is what the element and 8 registers. and 8 indicates that for a forbidden control code values 101 and 050, and a zero value confirms the proper functioning of the device.

The signal from the output of the element And 8 is fed to the first input of the third adder 7 modulo two, and is also recorded on the leading edge of the sync signal SI to the trigger 9, from the output of which goes to the first information input of the control register 11, the second input of the adder 7 modulo two and second the inputs of the adders 3.1-3.11 modulo two groups. In case of malfunctioning of the device, a single value from the output of flip-flop 9 ensures the inverting of the bits of the 1pc, Zpp-12pp result on the adders 3. 1-3.1 1 modulo two. The convolution unit 4 modulo three and the adder 3.1 modulo two groups form on the inverse value of the result the inverse value of the control code. When the control blocks work correctly, one forbidden value is transferred to another, the inverse forbidden value of the control code and the signal at the output of the element And 8 confirms its single value, the third modulator two modulo two compares the signal at the outputs of the element And 8 and the trigger 9 and the result of the comparison is written on the falling edge of the SI sync signal to the control register 11 through its second information input. From the first and second outputs of the control register 11, signals SC 1 and IC 2 are taken, respectively, arriving at the first and second control outputs of the device. Signals control SC 1, rewritable in the register 11 control with the output of trigger 7, takes a zero value when

ten

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Claims (1)

proper operation of the device, and a single value indicates a malfunction of the device. The control signal CK 2 takes a zero value when the control unit is working correctly, which ensures that the signals compared on the third sum modulo two are matched 7. A single value of the CK 2 signal indicates an erroneous operation of the control units when analyzing the direct or inverse result values. I "with the formula of the invention 0 five The matrix squaring device containing the modulo three modulo block, the first and second modulo two adders, the element And and the matrix of n / 2 column cells and n-1 rows, where n is the number, the operand width, and each cell contains an adder and an element I, the first output of the adder cell of the i-th row of each column of the matrix is connected to the first input of the adder of the cell (n +) -th row of the same column of the matrix (i I, n-2), the output of the element AND of each cell matrix is connected to the second input of the adder of the same matrix cell, the first output is the total and the cells (n -1) -th row of the j-ro column of the matrix are connected to the third input of the adder of the cell (p-2) -th row (j + column of the matrix (j 1, n / 2-l), the second output of the adder cell i -th row of the j-ro column of the matrix (, nl) is connected to the third input of the adder of the cell (i -2) -th row (j +1) -th column of the matrix, the first inputs of the elements And the cells of the first (n - j) -x rows The j-ro column (j 1, p / 2) is interconnected and connected to the input of the j-ro bit of the operand of the device, the second input of the element And the cell of the i-th row of the j-ro column of the matrix (j 1, nj) is connected to input (i + j) -ro bit of the operand device, the first inputs d elements and the cells of the last (j -l) -x rows of the j-ro column of the matrix (for j 1) are interconnected and connected to the input (n / 2 + j) -ro of the device operand, the second input of the cell And the cell i row of the j-ro column of the matrix (i n-j + l, n-1, j 1) is connected to the input (j + i -n / 2) -ro of the device operand, the third input of the cell's adder (2j - 1) st line one 0 five 0 five 0 five the matrix column is connected to the input (j +1) of the device operand, and the third inputs of the cells of the even rows of the first column of the matrix and the first inputs of the cells of the cells of the first row of all columns of the matrix are connected to the input of the logical zero of the device, the third input of the cell's adder (n-1) -th row of the j-ro column (j 1) of the matrix is connected to the input (j + n / 2) of the device operand, the second bit output of the result, which is connected to the input of logic 10 2j-My and 2j +1) to the information inputs of the output register (j 1, iL / 2 - 1), the second output is the sum of the torus of the cell of the i-th row of the n / 2-th column of the matrix connected to the (i + n - 1) -th information input of the output regigra, (i), ( 2n-1) -th information input output register is connected to the first output of the cell adder (n-1) -th row of the n / 2-th matrix matrix, the outputs of the output register are connected to the first and third terminals  the outputs of the device corresponding to the zero device, the first and second-1c n .. - 1e, and also The three modulo three outputs of the convolution block are connected respectively to the first and second inputs of the first modulo-two adder, the output of which is connected to the direct input of the And element, the inverse input of which is connected to the output of the second modulo-two math, the first input of which is connected to the first output of the block convolution modulo three, characterized in that, in order to increase the reliability of the operation, a group of 2p - 1 modulo two adders, a third modulo two adder, a trigger and a control register, entered into the first digit about The device's peranda is connected to the first information input of the output register, the synchronized input of which is combined with the synchronizing inputs of the trigger and the control register and connected to the device's clock input, the second outputs of the accumulators of the first and second rows of the j-ro column of the matrix are connected respectively 20 25 thirty 35 , a. icutw c l to the first inputs of the corresponding adders modulo two groups, the second inputs of which are combined and connected to the trigger output, the outputs of adders modulo two groups, from the second to (2n-1) th are connected to the inputs from the first to modulo three, the output of the first modulo-two adder is connected to the second input of the second adder modulo two, the output of the And element is connected to the first input of the third adder n to the module two and the trigger input whose output is connected to the second input third modulo two and first the information input of the control register, the second information input of which is connected to the output of the third modulo-two adder, and the first and second outputs of the control register are the first and second control outputs of the device, respectively. 2j-My and 2j +1) information inputs of the output register (j 1, iL / 2 - 1), the second output of the adder of the cell of the i-th row of the n / 2-th matrix column is connected to the (i + n - 1) -th information input of the output regigra, (i), (2n -1) -th information input of the output register is connected to the first output of the cell adder (n-1) -th row of the n / 2-th matrix column, the outputs of the output register are connected to the first and from the third to nenno as well as , a. icutw c l the first inputs of the corresponding adders modulo two groups, the second inputs of which are combined and connected to the trigger output, the outputs of the adders modulo two groups, from the second to (2n-1) and connected to the inputs of the first to () modulo three, the output of the first adder modulo two groups connected to the second input of the second adder modulo two, the output of the element And is connected to the first input of the third adder modulo two and the trigger input, the output of which is connected to the second input of the third adder modulo two and the first information input of the control register, the second information input of which is connected to the output of the third modulo-two adder, and the first and second outputs of the control register are the first and second control outputs of the device, respectively. aa VO "ABOUT I