SU1229755A1 - Device for multiplying in redundant number system - Google Patents

Abstract

The invention relates to computing and is intended for use in digital computers for various purposes. The purpose of the invention is to increase the speed of the multiplying device. The device containing the register, adder, and switch is entered (n + 1) one-bit multiplication nodes, where n is the size of the factors, and m are the bit registers, where m is the number of binary bits needed to represent one bit. multiplier, in the g-ary number system. In the proposed device, i.e. a quadruple excess number system is used. The one-bit multiplication node contains a table multiplier and adder in an excess quaternary number system. Each new bit is generated in two cycles. 2 Il. i (L to 1C ate

Description

The invention relates to computing and is intended for use in digital computers for various purposes.

The purpose of the invention is to increase the speed of the multiplying device.

Fig. 1 is a schematic diagram of a multiplication device in a redundant number system; 2 is a one-bit multiply node with a number).

The device for multiplying in the redundant numbering system contains one-digit nodes C, 1 ,, Ij, ..., 1b + 1 multiplication (OUU), t-bit registers - 2 ,, 2, -..., 2 inputs 3, , 4i, 5, 3

bS

four

managers 5 ". 3

a - i ъ

ъ 5з3 ,, D,,, 5, .first,

second, third ,, .., (n + 1) one-bit node 1 multiply, group: ny outputs 6, 6, 6, ..., 6j of the first, second, third, ..., (n + 1) one-bit one multiplication unit, group.

 g

7,,. . . , 7

th

transfer of the first, second, third, .., (PI; one-bit node of the multiplication, input X of the first device multiplier, input At the second device multiplier, the third group of inputs 8. ,, 8 ,, 83, 8j.i, the first , second, third, .., (n + 1) of a one-bit multiplication node, group of outputs 9, 9 ,, 9 ,,, ..,. izvest of the first, second, third ..., (n + 1) one-bit single multiply node, sync inputs} 0 ,,

10 „, 10,

10 t-bit d1x reg 2t

ditch, result register 11, synchronization input 11 - result register.

The one-bit multiplication node (figure 2) contains a tabular multiplier 12, a tabular adder 13, a first group of delay elements 14-16 a second group of delay elements 17-19, an adder 20 in a redundant numbering system, a switch 21, t-bit registers 22 and 23.

In the proposed device, a redundant number system with a base of 4 is used. In connection with which, to represent a single digit, three binary bits () are needed. The digit digits are encoded as follows: 0.11; .ten; 0.01;

.P ; .10% where D is a binary constant pointer

The numbers X and Y (multiplicand and multiplier) are bit by bit, starting from the senior ones, are post-input to the inputs X and Y, respectively. . On signals input to inputs 3, they are written

4 ,, first bits Zaouu 1

Where

the product XU is formed. In the second cycle, the second bits of the numbers X and Y are received. According to signal 3, bit X is recorded in the DTU, and simultaneously on signal 10, the first bit X from the DTU is written to the t-bit register 2. (in the further register), on signal 4 the second bit

The 5th number U is recorded in OUU K. V OUU

about.

five

0

0 5

five

0

1, the second and first bits are multiplied,. The generated zero bit npOH3Bej feHHH by signal 5 is supplied from the third bit output to the output bus, and by signal 11 is written to the register 1 1 of the result.

In the third clock cycle by the signal 3., the third bit X is recorded, in the OUU 1, by the signal Yu., The second bit Xj is recorded in the t-register 2, by the signals of the 3 bit D X., recorded

from the t-register cash 4j bit D OUU 1. In OUU 1

2, in ОУУ1

one

and is signaled to

t 3,

.J. In OSU 1, X is multiplied by Y and the formation of a bit is generated, the product of the discharge that appears. No signal 5., on the second bit output, OUU I 5 multiplies X, Y (X. x Y).

1 to

, bit Xj rewrites- 1, into w-register 2., by sig-, j-bit x, from t-register 2, and by signal- iOg bit x X-to-register 2. is formed in OUU

5ahl

In the fourth cycle, the signal 3 bit d X is recorded in OUU 1, signal} O with OUU on 3, OUU

written from OUU to Respectively OUU I, the product Y, while in OUU 1 the first bit obtained in OUU 1 is added to the transfer to .nepBbn i the discharge formed in OUU 1. Finally formed in OUU 2 The bit in the fourth clock cycle at the 5 "signal is fed to the third bit output and the hg signal 11" through the output bus is recorded.

In p

OZ T C, at the output of which a second bit is formed, and so on until the last single bit multiplication unit

in register 1.

tact in the work includes

Each new bit is formed in two cycles.

In the tabular multiplier 12, a multiplication table is recorded — in a redundant quaternary code. On the first and second outputs of the tabular multiplier I2, the transfer P is formed to the senior bit, which is fed to the first and second information inputs of the tabular adder 13. On the third, fourth and fifth outputs of the multiplier 12, the sum S is formed, which is received through delay elements 14-16 the third, fourth, fifth information inputs of the tabular adder 13, as the sum S. On the sixth, seventh and eighth address inputs of the tabular adder 3 of the previous VUU, the discharge of the product Sg is received. In the tabular adder 13 a table is written two quaternary digits (S,. ,, S) and carry (П,), At the first, second and third outputs of the tabular adder 13, the transfer P is formed, which is fed to the inputs of the adder 20. At the fourth, fifth and sixth outputs of the tabular adder 13, the sum Sj is formed, which through the delay delay, as the sum of 5 c, is fed to the inputs of the adder 20, the Last Represents the one-time adder for adding numbers in the redundant code.

The resulting sum of input bits is a two-digit number. The first bit is a carry to the most significant bit, it is added to the number stored in adder 20, and the resulting amount is output. The second bit is a prior current bit, which is corrected in the next clock cycle. The bit generated at the output of the adder 20 is fed to the input of switch 2. Depending on whether there is a signal 5 or not, the input information of the switch goes to output 6. (no signal) or output 7 (there is a signal), Input w-registers 22 and 23 are used to store the current digit numbers for the duration of the multiplication.

la invention

A device for multiplying in a redundant number system, containing a result register, a c-adder in a redundant number system and switching0

five

0

mountains, characterized in that, for speed purposes, n - registers are entered into it (n is the size of the factors), (n + 1) single bit multiplications, and the input of the first factor of the device is connected to the first group of inputs of the first a one-bit node, a group of outputs j-ro (j, 2, ..., n) of the first multiplier (i, 2, ... n) of a one-bit multiplication node is connected to the information inputs of the i-ro register, outputs which is connected to the first group of inputs (i + l) -ro of the one-bit multiplication node, the second group of inputs of the K-th (K 1,2, .. ,, n + 1) one-digit The multiplication node of the multiplication unit is connected to the second input of the second device multiplier, a third group of inputs of the first one-digit multiplication unit is connected to the device logical zero bus, the transfer output group i-ro of the single-digit multiplication unit is connected to the third group of inputs (i + l) -ro one time -R single multiplication node. TO,

 one

TO

TO,

the control inputs of the K-th single 3-bit multiplying node are connected

with the synchronization inputs of the device, the synchronization input of the i-ro register is connected to the i-th synchronization input of the device, the wake group of the i-ro bit is the product of the K-th single-digit multiplication unit of the connection 35 with the information inputs of the result register, the one-bit multiply node contains a table multiplier and adder, six delay elements, an adder,

40, the switch and two registers whose inputs are (respectively, the first and second groups of inputs of the one-digit multiplication node), the outputs of the first and second registers are connected to the first and second groups of information inputs of the table multiplier, respectively, the group of transfer outputs to the most significant bit of the table the multiplier is connected to the first group of information inputs of the tabular adder, the group of outputs of the partial multiplication of the tabular multiplier is connected to the inputs of the first, second and third delay elements, moves

55 of which are connected to the second group of information inputs of a tabular adder, the group of transfer outputs of which is connected to the first group of information inputs of the adder, the group of sum outputs is connected to the fourth, fifth and sixth elements of the delay, the outputs of which are connected to the second group of information inputs

Order 2450/48: Circulation: 671: Code Code of the VNIZhSh, USSR State Committee

for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5

Production and printing company, Uzhgorod, Project 4 st.

an adder, the outputs of which are connected to the inputs of the switch, the control inputs of the first and second registers and the switch are the control inputs of the one-bit node.

Claims (1)

Claim A device for multiplication in an excess number system containing a result register, an adder in an excess number system and a switch, characterized in that, in order to improve performance, η-registers are introduced into it (n is the digit capacity of the factors), (n + 1) one-bit multiplication nodes, wherein the input of the first device multiplier is connected to the first group of inputs of the first one-bit multiplication node, the group of outputs of the jth (j = l, 2, ..., π) discharge of the first factor i ~ ro (i = = 1,2, ... η) of a single-bit multiplication node is connected with information in the i-ro register moves, the outputs of which are connected to the first group of inputs (i + l) -ro of a single-bit multiplication node, the second group of inputs of the K-th (K = 1,2, ..., n + 1) single-bit multiplication node is connected with the second input of the second device factor, the third group of inputs of the first one-bit multiplication node is connected to the logical zero bus of the device, the group of transfer outputs i-ro of the one-bit multiplication node is connected to the third group of inputs (i + l) -ro of the one-bit multiplication node, K ,, K 1 _<3, the control inputs to the second one-bit multiplication unit connected the synchronizing inputs of the device, the synchronizing input of the i-ro register is connected to the i-th synchronizing input of the device, the group of outputs of the i-ro category of the product of the Kth 'one-bit multiplication node is connected to the information inputs of the result register, while the one-bit multiplication node contains a table multiplier and an adder , six delay elements, an adder, a switch, and two registers, the inputs of which are, respectively, the first and second groups of inputs of a single-bit multiplication node, the outputs of the first and second registers with are dyna with the first and second group of information inputs of the table multiplier, respectively, the group of outputs of transfer to the senior bit of the table multiplier is connected to the first group of information inputs of the table adder, the group of outputs of the partial product of the table multiplier is connected to the inputs of the first, second and third delay elements, the outputs of which are connected with the second group of information inputs of the tabular adder, the group of transfer outputs of which is connected to the first group in s formation inputs of the adder, the group of outputs of the sum is connected to the fourth, fifth and sixth elements of the gates, the latches, the outputs of which are connected to the second group of information inputs of the adder, the outputs of which are connected to the inputs of the switch, the control inputs of the first and second registers and j of the switch are control inputs single bit unit.