SU1137465A1 - Squaring device - Google Patents

Abstract

A SQUARE FOR SQUARE IN SQUARE, containing a group of elements AND, accumulating an adder, the bit inputs of which are connected respectively to the outputs of the elements AND group, characterized in that, in order to reduce hardware costs, the device contains a shift register, the output of the i-th bit of which ( i 1, П -2, where p - the width of the number squared is connected to the first input of the th element of the group, direct output (the n-th bit of the shift register is connected to the first input of the n-th element of the And group , inverse output ((n-1) -th register register shift is connected to the first input of the (n-1) -th element of the AND group, the second inputs of the AND elements of the group are combined and connected to the output of the n-th shift register register, the shift input of the register is connected to the recording input of the Daladir accumulator and the clock input of the device, information the input of which is connected to the information input of the shift register.

Description

(g - n: The invention relates to computing and can be used in the design and development of specialized and universal digital computers. A device for squaring, containing a n-bit base register, pulse distributor, a group of g elements, is known. I-NOT, (u-2) groups of elements I with m elements in each (- k) with 1 even u (t) with k odd, where Ic is the number of the group of elements And k k l- (ti -2), n - bit summator 1}. The disadvantage of this device is the high consumption of equipment. Its close technical essence to the invention is a device for squaring, containing: a register, an adder and a group of elements AND, the output of the i-th register bit being connected to the input of the (2i-I) -th digit of the adder, the outputs of the -th and j-ro bits of the register (ji +1, i + 2, ..., n) are connected by elements And are connected to the (i + j) th bit of the adder 2. The disadvantage of this device is the high consumption equipment due to the use of a large number of elements And (approximately P, „adders doubled length. The purpose of the invention is to reduce hardware costs. The goal is achieved by the fact that a device for squaring, containing a group of elements AND, accumulating an adder, the bit inputs of which are connected respectively to the outputs of elements AND of a group, contains a shift register, the output of which i-ro is (, h-2 where the p-width of the number squared is connected to the first input of the I-ro element AND group, the direct output (ti-l) -ro bit of the shift register is connected to the first input of the i-th element And group, inverse output (-1) -th bit of the shift register is connected to the first input of (nl) -ro element These AND groups, the second inputs of the AND elements of the group are connected and connected to the output of the n-th digit of the shift register, the shift input of the shift register is connected to the recording input of the accumulating adder and the clock input of the device, whose information input is connected to the information input of the shift register. The drawing shows a diagram of the device. The squaring device contains a clock input of the device 1, a shift register 2, an information input of the device 3, a group of elements AND 4, an accumulator adder 5, an output of the lower bits of the device 6, an output of the higher bits of the device 7. The accumulator adder 5 is a register sums and combinational adder. The outputs of the sum register are connected to the inputs of the combinational adder with a shift of two digits to the left. The device works as follows. To find the square of the number you need to perform n cycles. In the initial state, the shift register 2 and accumulating adder 5 are reset to zero. First cycle At device 3, the least significant digit of the number squared, X, and the clock input 1, signal C are supplied. Bit X is recorded in the h-and bit of the shift register 2, passes through the element And (4 1 group and enters the input (p-1 of the 1st bit accumulating adder 5. The second cycle. To the input 3 is fed the second bit of the number X2 and to the clock input 1 signal C. The bit d X is written to the (n-1) th bit of the shift register 2, X2 is written to h-ii bit from the input of the (n-1) th bit of the accumulating adder 5. Formed in the previous cycle, bit X is written to (n-1) the bit register of the sum of adder 5 and from there it goes to the input of the (n-3) th bit of the adder 5. As a result, sum Ator enters the conjunctions (in the p-th bit) and (in () -th bit). The third cycle. At the inputs of the device 1 and 3 are sent C- and X, respectively. The content of the shift register 2 is shifted by one bit. the adder receives the conjunction XjXj in the n-th bit.

311374654

XjXj in (p-1) -th discharge, .- c.7, the younger ones - from the output of device 6, (n-2) -th discharge,. Thus, the introduction of shifts

Similarly, the performed register allowed to reduce the apparatus

and the remaining c-3 cycles. After completion costs due to reduction

the last n-th cycle of a cycle in the na-numbers of elements AND groups from the order

the cumulative adder 5 will write ni approximately into us n the most significant bits of the square of the number 2

X. g, the least significant digits of the square of the number of speed of the invention, are output from the adder 5. Older, 2

square bits are read out the output is not inferior to the prototype.

Claims (1)

DEVICE FOR ESTABLISHMENT. SQUARE, containing the group of elements AND, accumulating the adder, the bit inputs of which are connected respectively to the outputs of the elements And groups, characterized in that, in order to reduce hardware costs, the device contains a shift register, the output of the ith digit of which (j = 1, η -2, where η is the bit capacity of the number squared) is connected to the first input i of the ith element of the group, the direct output of the (n-1} th digit of the shift register is connected to the first input of the n-th element of the group, the inverse output of the (n-1) th digit of the shift register is connected to the first input of (n-1 ) th element AND groups, the second inputs of elements AND groups are combined and connected to the output of the ηth digit of the shift register, the input of the shift reg Istra is connected to the recording input of the accumulating adder and the clock input of the device, the information input of which is connected to the information input of the shift register. > 1 1137465 2