SU875376A1 - Device for determining maximum from m binary numbers - Google Patents

Description

The invention relates to automation and computing and can be used in digital computers. A device is known for extracting an extreme of nm bit binary numbers, containing nm input elements OR, nm bit registers, m three-input elements AND, and one m input element OR for each of binary numbers. The direct outputs of the registers are bitwise connected to the inputs and input elements OR PZ. A disadvantage of this device is complexity. The closest in technical essence to the present invention is a device for comparing mn of bit numbers, consisting of OR elements, n "comparison blocks, mn sequential interrogation block and display unit 2. A disadvantage of the known devices is complexity. The purpose of the invention is to simplify the device. The goal is achieved by the fact that in the device for determining the maximum of binary numbers there are m groups of elements AND, m groups of memory elements, m groups of elements OR, multiple input highs OR, control khtsie elements AND, result register, charge elements, and the start control input device operation is connected to the first input of the first control element I and to the input of the first delay element, the output of each I-th delay element, where, 2, ..., (n-1), n is the number of bits of the numbers being compared is connected to the first input (i +1) - About control element I and to the input (i + l) -ro of the delay element, output (nl) -ro of the delay element connected to the output bus of the device, the output of each j-ro control element I, where, 2, ..., n is connected to the information input j-ro of the result register, the inverse output of each first memory element of the K-th group, where, 2, ..., t is connected to the first input of the first element of the K-th group, the output of the X of which connected to the installation input to the zero state of the second memory element of the K-th group and to the first input of the first element of the OR-th group, output ka; adogo P-th element OR each

K-th group, where, 2, ..., (p-2) is connected to the first input (P + 1) of the element OR K-th group, the output of each 1st memory element of the K-th group, where, 3 ,.,. (p-1) is connected to the first input of the 1st element AND of the K-th group, the output of which is connected to the second input of the (1-1) -th element of the OR of the K-th group, direct output of each i-ro of the memory element of the K-th group is connected to the K-th input of the i-ro multi-input element OR, the output of each of which is connected to the second input

The i-ro of the control element I, the output of each i-th control element I, is connected to the second and the inputs

i-th elements And all groups.

The drawing shows a block diagram of the proposed device.

The device contains m groups of elements, 1, ..., i ;, 1, 1 |, ...,

, ...,, 1, ..., 1 ;;, m groups of elements OR 2i (, 2, ..., 2.2 2, 2, .. 2., ..., 27, 25 ;,.. ., 2; j22 groups, memory elements 3, Sn,., 3,

s1E -ollloni om my mot-oJ, ..., Jf ,, ..., J, qj, .., a lot

input elements OR 4, 4 ,. . . , 4vi, control elements And 5, 5, j, ..., 5 "delay elements 6, 6 / i ,. .., 6 ,. , control input 7 start of work, output bus 8 device ,, register 9 re-result.

The device works as follows.

Before starting operation, the result register 9 is reset to the zero state, as well as all the elements of the 3 memories before receiving the numbers. Elements 3 of the memory are entered into mn-bit numbers and the device receives a pulse of operation start at input 7, which allows the signal to pass through the control element AND 5 to the first most significant bit, to the first input of which a multi-input element OR 4 is connected, associated with direct outputs of memory elements 3 of the same-bit bits of all numbers. If a unit is recorded at least in one memory element, the signal through the OR element 4 and the AND 5 element enters the result register 9 and records the unit in this bit as well as the second inputs of the And 1 elements of this bit. If the i-th (,. M) number of this bit is zero, then from the inverse output i-r6 of element 3 of the memory of this bit the resolving potential is removed, the opening element I 1 and all the elements 3 of the lower-order memory - The first number through the elements OR 2 receives a signal that resets them to the zero state. Thus, this number is excluded from the search process. The signal of the control element AND 5 is fed to the next delayed element b, which provides a delay of the signal for the switching time of one bit.

3 memory elements. The signal from it arrives at the AND 5 element of the next least significant bit only after the operation of the vani of the memory element 3 of all non-maximal numbers found in the | th cycle. Thus, the surviving numbers are polled for the presence of a unit in the next lower order. If no number in this bit de i-e contains ones, then the erasure of information does not occur, so. as the permit signal is not removed from the OR 4 element, and all numbers are stored. A device for extracting a maximum number of m binary numbers repeats the operations described p times. As a result, the end of the operation is formed on the output bus 8 of the serially connected (p-1) delay elements 6, and the result register 9 contains the maximum number of memory elements written in the elements 3. Recording the maximum number occurs at the same time, starting with the highest bits. Thus, the proposed device allows us to simplify the structure of the 5 RU by reducing the number of logic elements used in the device.

Claims (2)

1. USSR author's certificate №514291, cl. G About F 7/02, 07/06/76. 2. USSR author's certificate No. 526878, cl. G 06 F 7/50, 10/20/76 0 (prototype).