SU1520595A1 - Associative storage - Google Patents

Abstract

The invention relates to computing and can be used as associative memory devices in systems where it is necessary to conduct an associative search for an arbitrary number of features. The purpose of the invention is to expand the functionality by providing a search for information that is close in content to the input information. The device contains a matrix drive 1 consisting of memory elements 2, adders 3 and registers 4. 2 Il.

Description

The invention relates to computing and can be used as an associative storage device (memory) in systems where it is necessary to conduct an associative search for an arbitrary number of features.

The purpose of the invention is the expansion

05954

However, arrays A and B are stored in this memory in an addressless way, since the element of these arrays took part in the formation of several elements of array C, i.e. distributed over the entire volume of some part C, or array B is filled in array C at address A, Matching array (recovery)

device functionality-. It is not a call to address.

20

va by ensuring the search for information that is close in content to the input information.

FIG. 1 shows a schematic diagram of the assriative storage device; in fig. 2 is a block diagram of a memory element.

The device contains (Fig. 1) a matrix accumulator 1 tchp (where m is the number of rows; n is the number of columns of the matrix), consisting of memory elements 2, adders 3 — by the number of columns; connecting the information inputs and outputs of the device 25, the second information bus 6 connecting the indicative inputs of the device, write enable bus 7, read permission 8, reset bus 9, output buses 10, setup input II, receive input 12 and setup entry 13.

Each memory element 2 contains (FIG. 2) a comparison unit 14, elements 15 and 16, elements 17 and 18, a reversible counter 19, a group of elements 20 and a multiplexer 2J.

The device performs associative addressless processing.

A mathematical model of associative addressless processing is as follows. The input information is array A, the output information is B. The arrays A, B are sets of numbers tl. Let A be a column vector, B a row vector:

(x); (y) .1, ()

where, 2m;

, 2n.

It is necessary to write in the memory a correspondence to the input array A of the output array B. The result of this correspondence is the array-matrix C, and the elements C are the products of the corresponding elements of the input and output arrays.

C (x, y) a (x) -b (y). (2)

Array C is stored in memory in an addressable manner, i.e. each element is assigned a separate cell.

40

50

55

su, and the chain of transformations. Let there be an array

) 7; (3)

 C; (4)

where A is a row vector, transported vector A.

L (Y) T, C (x, y) .a (x). (5) Substituting expression (2) into (5), one obtains

L (V) - Zs / (x) -b (y).

(6)

Since the elements of the array A units

2,

With different signs, then the number a is one. therefore

/З (У)М.Ь (У), th М -Ь

-X there is

those,

(7) (8)

Formula (7) shows that the elements of an array are p-integers M with different signs, and for arrays 9 and B elements having the same numbers have the same signs, Therefore

B (y) (y)

-one,

if (b (y) o;

0 if / i (y) 0j

1 if /} (y) 0.

Let there be K pairs

Aq, B (, ..., K). All arrays of A are the same size as A, and all arrays of B are the same as B. Then array C is formed in this way

C- I CK-Z AK-B; (ten)

TO"

Restore the array / s

45, З, С,) А: (С ,,) С; + А:; (|: - c,) M B, -fW ,,

where W is the interference array.

If we choose array A so that M is even and the number of elements of any pair of arrays A and AI with different signs (code distance due to Hamming) is 1/2, then all elements of the array W will become equal 0 (k, 2 ,. .., K;, 2, ..., K;).

Array C establishes a correspondence between sets of codes A and B.

su, and the chain of transformations. Let there be an array

) 7; (3)

 C; (4)

where A is a row vector, transported vector A.

L (Y) T, C (x, y) .a (x). (5) Substituting expression (2) into (5), one obtains

L (V) - Zs / (x) -b (y).

(6)

Since the elements of the array A units

2,

With different signs, then the number a is one. therefore

/З (У)М.Ь (У), th М -Ь

-X there is

those,

(7) (8)

Formula (7) shows that the elements of the array p are integers M with different signs, and for arrays 9 and B the elements having the same numbers have the same signs, Therefore

(y)

-one,

if (b (y) o;

0 if / i (y) 0j

1 if /} (y) 0.

(9)

Let there be K pairs

Aq, B (, ..., K). All arrays of A are the same size as A, and all arrays of B are the same as B. Then array C is formed in this way

C- I CK-Z AK-B; (ten)

TO"

Restore the array / s

, З, С,) А: (С ,,) С; + А:; (|: - c,) M B, -fW ,,

where W is the interference array.

If we choose array A so that M is even and the number of elements of any pair of arrays A and AI with different signs (code distance due to Hamming) is 1/2, then all elements of the array W will become equal 0 (k, 2 ,. .., K;, 2, ..., K;).

Array C establishes a correspondence between sets of codes A and B.

Such a cooTBercTBvie exists when training the C array for any number of pairs. When the number of pairs changes, the conformity and its content also change.

Associative g memory device works as follows.

There are two modes of operation: Write and Read.

In Record mode (Training). Before starting work, each counter 19 must be reset, for this a negative impulse is sent to bus 9.

On bus 5, an n-bit word is set corresponding to vector 9 On bus 6, a t-bit word is set corresponding to vector A. Each i-th bit of word A is compared by comparison block 14 with j-bit word of ft ( , n;, m). A positive impulse through the write resolution bus 7 goes to the corresponding inputs of all the elements of the 2 memories. If the compared signals are opposite, then the output level of the element 16 is set to a low level, and the output of the element 18 is set to a high level,

the cut element And 15 passes positively with the fact which information

a pulse that, inverting the echo on the element NOT 17, excites the first counting input of the counter 19, and a counting down occurs.

one

If the compared signals are the same, then, similarly, by means of the AND 15 and HE 17 elements, a high level is established at the first counting input of the counter 19, and a negative impulse comes to the second counting input, and a direct counting occurs; Information is stored and accumulated in each counter 19 of memory element 2. The contents of all counters 19 elements 2 of the memory of matrix storage 1 correspond to matrix C.

This is how learning takes place.

on one couple of words. If such pairs are K,

elements of the memory 2 is involved in the process of summation. The P input of each adder 3 enters through bus 10 that bit of the number A, which corresponds to the row of the matrix accumulator 1. Upon completion of the summation process, the required output number B is formed at the outputs of the sign bits of registers 4. The number 40 is installed on bus 5.

Claims (1)

Invention Formula 5 An associative memory device containing a matrix drive consisting of. memory elements, where the information inputs of the memory elements of each column are matrices; a similar procedure is repeated after the last accumulator is combined and is K of the corresponding information input of the device; the inputs for recording the memory elements of each row matrix drive combined and At the same time, the capacity of the counter corresponds to the number of trained couples, and the highest bit should be significant. If necessary, you can increase the corresponding input by splitting the counter size using the device's recording solutions, the inputs of the forward and reverse reading outputs of the iam-i-transcend elements. 15 , 0595 In the Read (Restore) mode, before starting the work, the registers 4 are reset. Bus 6 exposes a t-bit dns e. Word A. Each element 2 of the memory receives a signal corresponding to one of the word bits A. The same signal goes to the address input of the multiplexer 21. If it opens the first channel, the output bus 10 is connected to the outputs of the elements HE 20, if the second channel opens, the output bus 10 is connected to the outputs of the counter 19. The memory elements 2 included in the column of the matrix drive 1 have a single output bus 10. Sum the numbers 20 arriving on the output bus 10, and the numbers in register 4, is produced when a recording signal arrives at the input 12 of the receive. The summation is performed m times, it occurs in parallel in columns and successively in rows of matrix accumulator 1. In this case, the lines constituting the read resolution bus 8 are excited sequentially in accordance with the elements 2 of the memory involved in the summation process. The P input of each adder 3 enters through bus 10 that bit of the number A, which corresponds to the row of the matrix accumulator 1. Upon completion of the summation process, the required output number B is formed at the outputs of the sign bits of registers 4. The number 40 is installed on bus 5. Invention Formula 5 An associative memory device containing a matrix drive consisting of. memory elements, the information inputs of the memory elements of each column of the matrix-matrix accumulator are combined and are the corresponding input of the write resolution of the device, the inputs of the resolution of the readings of the elements are unified and are the corresponding input of the read permission of the device, characterized in that, in order to expand the functionality of the device by providing search for information similar in content to the input information, adders and registers are entered into it, and the information inputs of each register are connected to the outputs of the corresponding adder , the register receive inputs are combined and are the device input of the same name, the register setup inputs are combined and are the first device installation input, you The moves of the sign bits of the registers are information outputs of the device, the outputs are information editor O. Golovach Compiled by, Rudakov Tehred L. Serdyukova Proofreader. H, King Order 6765/54 Circulation 558 VNIIPI State Committee for Inventions and Discoveries at the State Committee on Science and Technology of the USSR 113035, Moscow, Zh-35, Raushsk nab., A / 5 the mapping bits of each register are connected to the information inputs of the first group of the corresponding adder, the same name outputs of the memory elements of each column of the matrix accumulator are combined and connected to the corresponding inputs of the second group of the corresponding adder, the indicative inputs of the memory elements of each row of the matrix accumulator are about & are the corresponding attribute input of the device, the reset inputs of the memory elements of each row of the matrix drive are combined and are the corresponding input reset of the device, the installation inputs of the memory elements are combined and are the second installation input of the device. Subscription