SU920832A1 - Storage device - Google Patents

Description

(54) STORAGE DEVICE The invention relates to computing technology and can be used in the development of single-chip BIS chargers and the construction of operational memory systems of various devices on their basis. A memory device is known, which is a linear array of arbitrarily addressable cells containing a series of one-bit semiconductor memory units, which are connected in parallel to addresses and control buses G1. Closest to the proposed technical essence is a storage device containing. one-bit memory blocks, connected in parallel via address buses | and control buses Read / Write Sample the address of the column, Sample and row addresses, where the information word is fed in parallel to the information inputs and read from the information outputs of the memory blocks. We use in this memory system the memory blocks contain J9e encoders row and column addresses, a matrix of storage elements, a read amplifier and I / O fields, a control node 21.. Such memory systems exclude the possibility of parallel reading / writing for one cycle of operation of the same-named word bits in adjacent memory cells, since the data of the same-name bit is located in one memory block. In a number of problems of matrix algebra, as well as in information-logic problems operating with tables, such a requirement arises. The purpose of the invention is to expand the functionality of the memory system by enabling the writing and reading of the same-named word group bits. This goal is achieved by the fact that in the memory device containing memory blocks, the address and control inputs of which are respectively the address and control inputs of the device, a switch is entered, some inputs of which are connected to the outputs of the memory blocks, and the other inputs of the switch information inputs of the device, a cyclic shift unit, one inputs of which are connected to the switch outputs, and outputs to information inputs of the memory blocks, and a register whose inputs are connected to the address

the inputs of the memory blocks, and the outputs to the other inputs of the cyclic shift unit, the control inputs of the switch and the cyclic shift unit are the corresponding control inputs of the device.

In addition, the memory block contains a matrix drive, row address and column address decoders, a switch, a reader amplifier unit, and a control unit whose address and control inputs are the address and control inputs of the memory unit, respectively, and the decoder inputs. the addresses of the row, the decoder of the column addresses are connected to the corresponding address outputs of the control unit, the information outputs of which are the information outputs of the memory block, the outputs of the column address decoder are connected to the inputs of the block read silica cells, one output of which is connected to the information input of the control unit, other outputs of the readout unit are connected to the corresponding inputs of the matrix accumulator, outputs of the row address decoder are connected to the switch inputs, the outputs of which are connected to the corresponding matrix inputs of the matrix accumulator, the control input of the switch is control memory block input.

Fig. 1 shows a block diagram of the memory device of Fig. 2: a functional diagram of a memory block; Fig. 3 shows the order in which the information is located in the storage device.

The memory device contains one-bit memory blocks 1, an n-bit switch 2, a cyclic shift block 3, and a register 4 for storing k lower-order address bits, yugs control inputs 5 Column address sampling, control input b control input 7 read / write, address inputs 8, control inputs 9 memory blocks, information inputs 10 and. information. 11 device outputs.

In addition, each memory block 1 contains a row address decoder 12, a column address decoder 13, a matrix accumulator 14, a read amplifier block 15, a control block 16 and a switch 17, control inputs 18-20, address inputs 21, information V350DY 22 and 23, however, with a cyclical upward shift, the offset value is determined by the position of the memory unit), the control input of the switch 17 and the control input 24 Horizontal / Vertical.

The device works as follows.

The cyclic shift unit 3 shifts the information block while recording to the left. The outputs of the decoder 12 in the memory unit are connected to the corresponding first inputs of the switch 17 with a natural order of their following and to the second inputs with a cyclic shift upwards. The offset value is determined depending on the position of the memory block and is (i-l) entier - provided that

, i s i, 2, ..., n, where n is the cell width of the memory system, m is the number of outputs of the line address decoder, I is the position number of the memory unit.

Logically, the memory is a linear sequence of elementary matrixes of bits, the dimension of php. Accordingly, the logical cell address of the memory system is indicated by two fields defining the number of the matrix of bits A in the memory system and the number of the cell A in the matrix. Tires of address A are registered on register 4

There are four possible modes of operation of the PSMI system: writing the information word (I), reading the information word (II), writing the like bits of words (1M), reading the like bits of words (IV),

Modes differ from each other only by a combination of control signals at inputs 7 and 9. Therefore, in order to clarify the principle of operation of the system, it suffices to consider modes I and IV,

The mode (. The signal Horizontal / Vertical at input 9 is equal to O. The address of the memory device is set to the address of the line and stored in the memory blocks by the signal at input 6. At the same time, the address A field in the register 4 is memorized by the same signal. Block 3 cyclic shifts, depending on the contents of register 4, are adjusted to cycle the information word by an appropriate number of bits.

Then, similarly, it is fed and entered into memory blocks by a signal at input 5 of the cross-column.

On the read / write signal at input 7 equal to 1, the information word, prior to modifying / 1 but set to the information inputs 10 of the device, through the switch 2 is fed into the cyclic shift unit 3 and then shifted to the right by the required number of bits, goes to information inputs of memory blocks 1 ". The same signal will write to the memory blocks.

Claims (2)

The order of the location of the information in the storage device is according to. its logical representation is shown in FIG. 3, where A, B, C, D, E are words stored in a memory. Mode IV. The signal Horizontal / Vertical is equal to 1. In the initial position, the input 7 Read / Write is O, which corresponds to the reading mode. In the same way as in mode I, row and column addresses are alternately set to Hot inputs 8 and the signals at inputs b and 5 are stored in memory blocks. By the signal at input 6, the address field A is also entered into register 4 and block 3 cyclic shifts are adjusted to shift the read word-left. All memory blocks accept the same address. However, as a result, the displacement of the switch 17 by the signal Horizontal / Vertically equal to 1 of the outputs of the decoder of 12 lines of the line, in each block 1 of the memory, the bits are also selected with an offset. The offset value is determined by the position of the memory block. If N is the position of the bit corresponding to the supplied address, then in memory blocks 1, the bits from the poiCtion + E (1 -1) eP t ie i, where V is, are the number of outputs of the decoder 13 column width, i.e. if the memory topic is an address 00 ... 00. Or . .01., The word bnCrt will arrive at the outputs of memory 1 blocks after reading. .. BI, which is shifted in block 3 of the cyclic shift by one bit to the left and at the outputs of the memory system 11 stands. .. (see Fig. By expanding the functionality of the memory system in computing devices, it is possible to implement a number of new algorithms for scientific and technical, as well as information and logic problems, using the principle of processing information words in parallel by words and sequentially Formula of the invention 1. The storage device, containing memory blocks, the address and control inputs of which are respectively the address and control inputs of the device, is that to expand and the functionality of the device due to the possibility of recording and reading the same-word bits of a word group, it contains a switch, some inputs of which are connected to the outputs of memory blocks, and other inputs of the switch are information inputs of the device, a cyclic shift block, some inputs of which are connected to the outputs the switch and the outputs to the information inputs of the memory blocks, and the register, the inputs of which are connected to the address inputs of the memory blocks, and the outputs to the other inputs of the cyclic shift unit, which control The switch and cyclic shift block moves are the corresponding control inputs of the device. 2. The device according to claim 1, wherein the memory unit contains a matrix drive, a row address decoder and a column address decoder, a switch, a reader amplifier unit and a control unit whose direct and control inputs are respectively addressable. and the control inputs of the memory block, the inputs of the row address decoder, the column address decoder are connected to the corresponding address outputs of the control block whose information outputs are the information outputs of the memory block, the outputs of the decoder ad The column is connected to the inputs of the reader amplifier unit, one output of which is connected to the information input of the control unit, other outputs of the reader amplifier unit are connected to the corresponding inputs of the matrix drive, the outputs of the address address decoder are connected to the inputs of the switch, the outputs of which are connected to the corresponding inputs of the matrix drive, controls the switch input is the control input of the memory unit. . Sources of information taken into account in the examination 1. Electronics, 1974, 9, o.59. 2. Electronics, 1976, 4, p.4 Prototype). w w 2D 21 22