SU1543460A1 - Device for correction of information in permanent memory units - Google Patents

Abstract

The invention relates to computing and can be used to correct information in the blocks of permanent memory. The purpose of the invention is to simplify the device. The device comprises a memory 4, a code conversion unit 5, a multiplexer 6, a memory block of the equalizer 7, an output multiplexer 8. Introducing the multiplexer and its connections with the memory block of the corrector and the code conversion unit simplifies the device. 1 hp f-ly, 2 ill.

Description

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The invention relates to computing and can be used to correct information in the blocks of permanent memory, made-, for example, on masked BIS ROMs. The purpose of the invention is to simplify the device.

Figure 1 shows the block diagram of the device; Fig. 2 is a block diagram of a " conversion unit.

The device contains the first 1, second 2 and third 3 groups of address buses, drive 4, code conversion unit 5, first multiplexer 6, corrector memory block 7 second multiplexer 8, information devices 9.

Code conversion block 5 contains the first 10, second 11 and third 12 drives.

We consider the device operation by the example of correction in the storage 4 with the information capacity of 256 K words with 6 bits each, up to 8000 arrays of information with 4 words each, which can be located in arbitrary places of the address space. Three of this, we believe that the drive 4 is made on masked BIS ROMs, such as 541PE1, 563PE1, etc., organizing 3 K words in 8 bits, and the code conversion and t-opa correction blocks are made using

burned BIS ROM, type 541РТ2, - 556РТ7, etc., organization 2 К words for 8 bits. Such a construction of a corrected memory allows for a long time to operate a block of permanent memory, made on masked

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VIS ROM, with errors in the programs and refuse the time-consuming and lengthy process of making new photomasks and launching into production of new crystals of masked BIS ROMs. The necessary changes to the program are made promptly, by the user, at the expense of the corresponding Kigani BIS ROM corrector and code converter.

The word width of the corrector memory block 7 is chosen equal to the width of the information words of the accumulator 4. The information volume of the corrector memory block 7 is determined by the number of correction arrays and their length. The number of bits first

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groups 1 of address buses are determined by the length of the correction array (for the considered mrpché of the example, a BOB length of 4 words is necessary 2 bits). The number of bits of the second group of 2 address busses is determined by the number of correction arrays in the memory unit 7 of the corrector (for

10 8000 arrays needed 13 bits). The number of bits of the address inputs of the code conversion block 5 is equal to the number of bits 2 and the third 3 groups of address buses and is determined by the number of arrays in drive 4 (for the case in question, drive 4 contains 64000 arrays, four words each, in connection with which bit depth second 2 and third 3

20 groups of address tires is equal to 16).

The third group of address buses 3 determines the number of zones in the address space of accumulator 4, equal in information capacity to block 7 of memory

25 corrections (for the case in question, the number of zones is eight).

One of the bits of the first accumulator 10 of the code conversion unit 5 contains a sign of the presence of correction for any given (on the second 2 and third 3 groups of address buses) array of control of the multiplexer 8, in addition, the second bit of information of this block

The g contains the indication of control by multiplexer 6. The second II and third 12 accumulators of the code conversion block 5 must have a total number of address inputs of at least first 40 in drive 10 and the total number of information outputs that are outputs of the second group of code conversion 5, equal to the number of bits of the second group of 2 address tires in relation to the case under consideration - 13).

The device works as follows.

When accessing address buses (, 2, 3) to drive 4, information read from it goes to the second input group of multiplexer 8. At the same time, if there is no correction in the information array at this address from the first output group of the code conversion unit 5 (from the output of the first block 10 memory) receives zero information on the control inputs of multiplexers-selecto30

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Ditch 6 and 8. As a result, information from the outputs of accumulator 4 passes to the outputs of device 9 through multiplexer 8 without changes.

If it is necessary to correct the information of accumulator 4 to the corresponding addresses of accumulator 10 (code conversion block 5), single information is recorded in the first information discharge, and in the second information discharge, single information is recorded when the addresses of subsequent corrected arrays belonging to other zones of the 4 sec. previously used (the zone number is given by the third group of address buses 3).

In the case of access to drive 4 and if there are corrections of information in arrays located in the same zone or in different zones of drive 4 and related to different (different) addresses within the zones, a single information comes from the outputs of drive 10 to the control input of the multiplexer 8 and null information to the control input of the multiplexer 6. As a result, the multiplexer will switch to the outputs of the device 9 and information will be received, read from the outputs of the corrector memory block 7 at the non-transformed address determined by the first 1 and second 2 groups of device address busses. The total number of thus adjusted data arrays for the considered example can reach 8000 arrays of 4 words each.

In the case of access to drive 4, if there are corrections of information in different situations and if a number of addresses of corrected arrays coincide within zones with previously used addresses from the outputs of accumulator 10 of the code conversion block 5, the unit inputs of multiplexers 8 and 6 will receive a single information. As a result, the data of the multiplexers will be switched and the information outputs of the device 9 will receive information read from the outputs of the memory block of the corrector 7 to the address determined by the information of the first group of address buses 1 and converted (on the second 11 and third 12 accumulators of the code conversion unit 5) a) information second 2 and third

3 groups of device address buses. At the same time, as a result of address conversion in block 5, arrays belonging to different zones of accumulator 4 and matching addresses (numbers) inside the zone will be assigned during correction to different addresses in the memory block of corrector 7 that do not match previously used (without conversion) the addresses of block 7 of the memory of the corrector, which ensures the fulfillment of the previously assigned task.

Claims (2)

1. A device for correcting information in blocks of permanent memory, containing a code conversion block § drive, first, second, third group of address inputs of which are connected to the corresponding inputs of the device, drive outputs of which are connected to the first information inputs of the first multiplexer, whose outputs are information You, by the device moves, the inputs of the block. The transformation of addresses is connected to the second 0 and third groups of the address inputs of the storage device, characterized in that, in order to simplify the device, to it the second multiplexer, whose outputs are connected to the first address inputs of the corrector memory block, whose outputs are connected to the second information inputs of the first multiplexer, the second address inputs of the corrector memory block are connected to the first group of address inputs of the accumulator, codes are connected respectively to the control inputs of the first and second multiplexers, the outputs of the converted code conversion code block are connected to the first information data inputs of the second multiplexer, the second information inputs of which are connected to the second group of address inputs of the drive. 2. The device according to p. Differs in that the code conversion block contains the first, second and third drives, whose address inputs are connected to the inputs of the code conversion block t, the outputs | the first accumulator are the first and second outputs of the correction signal 0 five 0 five 715434608 address translation block outputs are transformed code outputs the second and third drives of the VL address translation unit, I address translation block Schig.2