SU1300518A1 - Device for recognizing and accounting parts transferred by conveyer - Google Patents

Abstract

The invention relates to computing technology. The aim of the invention is to increase the reliability of recognition and consideration of details. The device comprises a part presence sensor, control units, counters, memory blocks, decoders, a comparison unit, a signal generating unit, a counter unit, a drive unit, a sensor unit, a calculation unit, and a display unit. In the invented step, the settings optimize the number of sensor pairs (emitter-radiation receiver) and the motion path of each pair during recognition, optimal for identifying each part in the set in the minimum number of steps. 6 hp f-ly, 12 ill. § (L

Description

The invention relates to computing technology, namely, devices for recognizing and accounting for parts, can be used in the automation of industrial processes for sorting and storing in mechanical engineering, instrument engineering and other fields.

The aim of the invention is to increase the reliability and the recognition of detail recognition.

Fig, 1 shows a diagram of the device; Fig. 2 is a diagram of the first control unit; FIG. 3 is a diagram of the first memory block; Fig. 4 is a diagram of the second memory block; Fig. 5 is a diagram of a second control unit; Fig. 6 is a diagram of the third control unit; Fig. 7 is a diagram of a third memory block; Fig. 8 is a diagram of the fourth memory block; Fig. 9 is a diagram of a signal generating unit; in fig. 10 is a block diagram display; Figure 11 is a block diagram diagram; Fig. 12 is a block diagram of the comparison.

The block diagram of the device in FIG. 1 contains a detail presence sensor 1, a first control unit 2, a first counter 3, a first memory block 4, a second counter 5, a second decoder 6, a sensor block 7, a sensor drive unit 8, a digital-analog converter unit 9 a second 10 memory block, a third decoder 11, a third counter 12, a fourth counter 13, a second control block 14, a third control block 15, a third memory block 16, a fourth memory block 17, a signal generation unit 18, a block 19 in; Calcations, Computation Block 20, Comparison Block 21, First Decoder 22, Counter Block 23.

The scheme of the first control unit 2 in FIG. 2 contains an OR 24 element, a start button 25, a pulse generator 26, AND element 27, a counter 28.

The diagram of the first memory block 4 in FIG. 3 contains operative storage units 29 ... 29p, the first toggle switch 30, the first element OR 31, the second element OR 32, the third element OR 33, the OR-NOT element 34.1 ... 34p, blocks subtraction 35.2 ... 35p, fourth element OR 36, elements And 37.1 ... 37p, second toggle switch 38.

Scheme of the second memory block 10. is represented in FIG. 4: permanent storage units 39.1 ... 39p, trig 10

hera 40.1 .., 40p, subtraction blocks

41.2 ... 41 p, elements OR 42. 1 ... 42 p.

The scheme of the second control unit 14 is shown in FIG. 3: the trigger 43, the first element AND 44, the first element OR 45, the second element OR 46, the pulse generator 47, the second element AND 48, the start button 49.

The scheme of the third control unit 15 is shown in FIG. 6: the elements And 50, the first decoder 51, the second decoder 52, the nepeKj reader 53.

The scheme of the third memory block 16 is shown in FIG. 7, the operational 5 storage units 54.1 ... 54p, the operational storage unit 55, the OR element 56.

The scheme of the fourth memory block 17 is shown in FIG. 8: operational 20 storage units 57.1 ... 57p, operational storage unit 58, first element OR 59, second element OR 60.

The circuit of the signal conditioning unit 18 is shown in FIG. 9; counters 61 of the number of parts, the first element OR 62, the decoder 63, the trigger 64, the register 65, the second element OR 66, the element 67 delay.

The diagram of the display unit 19 is shown in FIG. 10: the element AND 68, the resistor 69, the reg ister 70 the decoder 71, the indicator 72, the element OR 73.

The block of computation block 20 is represented in FIG. 11: subtractors 74, 35, driver 75 pulses, elements AND 76, decoder 77, element OR 78, comparison element 79 and address ka25

thirty

banks, each of which contains a register 80 accounting, the second element And 81, triggers 82, element 83 delay and adder 84.

The diagram of the comparison block 21 is shown in Fig. 12: register 85, the element OR 86, the switch 87, the first element AND 88, the second element AND 89, the element of comparison 90 and the start button 91.

The device works in two modes.

The first Setup mode is designed to determine the coordinates of the opti- mum positions of the sensors when a specific part is recognized in

set. In the second Operation mode, the device, using information obtained in the Configuration mode, performs the determination of the type of part and the consideration of the number of a certain type.

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for the minimum possible number of steps the minimum possible number of sensors for a given set of parts.

In the Setup mode, information is formed in the memory block 16 and in the memory block 17, which determines the optimal movement of the sensor pairs (emitter-receiver, pointed at each other) during recognition. The scientific research institutes of this part due to the fact that the coordinates of the subsequent movement depend on the information obtained from the sensors as a result of the previous movement, i.e. from the subgroup to which this part falls at each recognition step.

The number of subgroup sets is equal to the number of recognition steps. Parts are divided into subgroups depending on the code of information received from the sensors. In the Setup mode, the part that needs to be recognized is moved on the conveyor.

The principle of operation of the device is as follows.

When a part moves in the recognition zone, a step-by-step displacement of a pair of sensors occurs. The number of steps is determined by the time of movement of the part in the field of view of the sensors, i.e. meanwhile, during which the part remains distinguishable by this pair of sensors. The next position of the sensor is selected taking into account the fact that the part has already moved forward a certain distance.

If at the first stage during this time of movement in the zone of recognition the parts in the set remain indistinguishable by one pair of sensors, then at the next second stage of the Setup mode, a second pair is connected in the zone of recognition.

 Details are also viewed by the second pair, which increases the code spread. In this case, in the Recognition Operation mode, the parts of this kit simultaneously operate the first and second pairs of sensors.

If two pairs for parts recognition are not enough, then similarly at the next stages a third pair is connected to the recognition process, etc.

In Setup mode, the device works as follows.

Items in the set are arbitrarily assigned numbers identifying the type

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the details. The first stage of the setup is to collect information about the configuration of the parts. When a part enters the recognition zone, sensor 1 turns on a recognition device, generating a signal about the start of the recognition process, which is fed to control unit 2.

Block 2 passes the signal from sensor 1 to the first output and the counter 3 connected to it, the contents of which determine the row address of memory block 4 and control block 14.

Block 14 transmits, in the mode of this stage, a signal from the block of drives 8 of a pair of sensors to the counter 13 only by a signal, from the three output of the block 2 about the appearance of the part in the recognition zone and to the counter 5.

The counter name 13 determines the column address of the memory block 4. The contents of the counter 5 are controlled via the decoder 6 by the memory unit 4 and sets the coordinate address of the pair of sensors stored in the memory unit 10.

At the first stage of tuning, information is formed in the 4 ttami block. Block 4 includes n parallel-connected blocks of RAM 29.1 ... 29n, where n is the maximum number of sensor pairs. Each pair of sensors of block 7 is moved from a corresponding drive, which in block 8 of drives for the movement of sensor pairs is controlled by signals through block 9 of digital-to-analog converters, which is fed with information from the output of corresponding block 10.

The selection of cells in block 10 is performed by the decoder 11.

In the initial state, all counters are reset to zero. Block 39.1 is selected and the first row of block 39.1 of the first pair of sensors is addressed. From sensor 1, the signal enters counter 3 and the first line of block 29.1 is addressed. The signals from the sensor unit drive unit 8 are fed to the counter 13 through the block 14 and the address counter 5, and from the sensor block 7 to the input of the block 4 and for the first part in the line a code is formed in which the information in each bit corresponds to the information With a pair of sensors on the corresponding step. Then a signal is received from sensor 1: to the counter 3 about the appearance in the zone of the second part, increasing its contents by 1 and, therefore, the address of the next line of block 29.1, and the axis

There is a code generation for the second part from the first pair of sensors.

Similarly, the process occurs for the third, and so on. to the i-th part in the corpse ne.

In the next second setup step, the information generated in the memory unit is pre-processed. The memory unit 4 is set to a mode of communication. It is necessary to determine whether the codes differ in the rows of block 29.1. For this, a code analysis unit 21 is used, which operates as follows,

First, register 85. is rewritten via element 86 OR the first line. Switch 87 sets 1 at the second input of the first element 88 I.

Pulses from block 14 are supplied to the second inputs of elements 88, 89. After recording, switch 87 sets 1 to second input of element 89 and pulses from block 14 passes to the input of register 85. Comparison element 90 compares the string written in register and lines from block 4 and outputs mismatch signals to output 1 of the device and to block 16.

If the codes do not differ, then for all parts in the group, the codes are deformed in block 29.2. The second is turned on, the pair of sensors in block 7, and the first pair is turned off. After zeroing, the counter 13 starts counting from 1 and addresses the cells of the block 39.2 of the coordinates of the second pair of sensors, the block 39.2 is selected by the decoder 1 1 of the counter 12, counting the zero signals of the counter 13.

Counter 3 does not zero and select the next cell in block 4 and determines the columns from the number p + 1, where p is the number of steps of the sensor. The addition of the codes in block 4 is carried out similarly to the first stage.

Then, the distinguishability of the codes is reanalyzed and the number of dafchikov is consistently increased to those

until analysis block 21 generates a code mismatch signal.

In the third stage, the settings in block 4 exclude non-informative codes, i.e. columns containing only O or only 1, and of the same codes remain on one representative. In this process, exclude

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The sensor positions to which the addresses of the uninformative columns correspond correspond and the memory block 16 is formed.

The comparison of the column codes by the code analysis block 21 is carried out in a manner similar to the BTOpoisiy stage, with only

the difference is that column 85 is rewritten to register 85, and 0 or 1 to the input of register data 85 is fed by button 91.

Vlok 16 of the memory contains n blocks 54.1..54p, where n is the number of sensor steps remaining after elimination

non-informative provisions, i.e. the number of recognition work steps.

The number of RAM 55 in each subsequent set is 2 times greater than the number of RAM 56 in the previous set, where m is the number

sensors. Block 54.1 contains one RAM 55. The address inputs of all RAM 55 are combined and information from block 2 is supplied to them. Information inputs of all RAM 55 are combined and information from counter 5 is supplied to them.

The write / read inputs of all blocks 55 are combined and a write signal is supplied to them from the analysis block 21. AT

C1

no write signal blocks 55 are in read mode. The signal is input to the sample input of the block 55: from the corresponding output of the block 15. The information output from all the blocks 55 passes through the element 56 OR.

In the fourth adjustment step, subgroups of parts are selected and a corresponding position selection block 55 is formed for each subgroup. The subgroup of parts is distinguished by the value of the first K bits in the code. Subgroups are formed in memory block 17.

This block includes the set of RAM 57.1 ... 57.t. and the number of blo | j

58 in the i-OM set is 2 times the number of blocks in the (i-1) set. Block 2

The control sequentially generates the addresses of lines 1 through item. The bit data goes to block 15, which selects the corresponding blocks 58, which are in read mode.

In this case, the data input receives information from the counter 3 of the part number. Signals for address, fetch and write are fed to the inputs of block 58 in parallel with block 55. In the process of shaping, 71

No blocks 58 are used to form a recognition unique character column. The presence of a sign provides information that recognition is complete. The value of the sign is given to the output of the recognition system. If the number of parts in the corresponding block 58 is more than one, then the sign is not formed. If in block 58 one detail is recorded, then in this case block 18 eliminates the signals: the column addresses are 1 more than the number of bits in the part number, the data (value 1), the line address (value 1).

At the fifth configuration step, the codes are processed in block 58 in the same way as the third step with the only difference that it first looks at the first block 58 and the first block 55 of the second block 54.2 is formed for it. The codes of the second block 58 of the first block 57.1 are then processed and the second block 55 of the second block 54.2 is formed for it. The process of dividing into subgroups continues until all blocks 58 remain in one piece. In this case, block 18 is the signal to terminate tuning on exit 3 of the device.

In operation mode, the device operates as follows.

Sensor 1 receives a signal that a part appears in the recognition zone. The number of sensors needed to recognize parts of this group is included. In block 16 recorded column numbers corresponding to the value of the counter 5 addresses.

It is necessary to allocate one address optimal positions for the first, second, etc. k-ro sensors For this, the information recorded in memory block 16 is fed to calculation block 20, where, depending on the number of sensors and the number of steps, the addresses of the following ROM 39 corresponding to each sensor are determined, and all sensors are set to the next of which position. The corresponding coordinates through block 9 corresponding to each sensor are fed to block 8 of the drives. The sensors are moved to the first position and a signal is taken from the sensors of block 7, which is fed to block 15, where the analysis is carried out

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the code from the sensors, as a result of which block 58 and block 55 are selected, corresponding to a subgroup of this de-. hoists on this recognition step. , In block 58, the part number is addressed to a feature cell. When this block is sampled, the value cell of the feature is read and fed to the display unit 19, the input of which is the part number. If the sign is equal to O, then block 15 generates a signal allowing the selected block 55 to be found in optimal positions. The information enters the calculation block 20.

The following sensor positions are set to continue the part recognition process. If the sign is equal to 1, then the readout signal of the part number is generated, which arrives at the tripping inputs of the sensor drives and the display unit 19, which displays the number of the recognized part.

Accounting for details is carried out as follows.

The part number code is output from the memory block 17 and is fed to the decoder 6, which generates a signal at the input of the counter block 23, in which each type of component corresponds to a counter.

Signal signal selects the decoder 6.

Non-standard device units at various stages of operation function as follows.

The line address control unit 2 operates as follows.

In the setup mode, in the first stage, the signal from sensor 1 goes through element 24 OR to element 27 And and counter 28, the signal passes from generator 26 to counter 3. In the configuration mode in the following steps, the row address is generated from generator 26, for which the input element And logical 1 is established from button 25. From the output of element 24 1W, signals from sensor 1 and from button 25 are sent to control unit 14.

Control unit 14 is working next. this way.

In the first stage of the setup mode, from the block 2 of address line control to the trigger 43, the signal to start recognition II trigger 43 sets the input of the element 44 AND the logical 1, which passes

91

via element 45 OR signals. from block 8, fixing the step of movement of the sensors. In the following stages, in the setup mode, the signals from the generator 47 are received by the element 48 through the AND 48 element from the button 49 with latching.

Thus, at the output of the element 1 shina 46, pulses are formed, which go to blocks 5, 13, 21 and signals |

Block 10 works as follows.

In the sampling circuit of the 39.1 .., 39, k sensors, a trigger 40.1 ,,, 40.k is installed, which is set to one state by the decoder 11. If during the tuning process it became necessary to use K sensors, then the blocks 39 will be selected. As the 11 states of the counter 12 appear at the outputs of the decoder, the number of sensors is gradually connected to the work of the blocks 39 of the first pair of sensors, then the second pair, and so on, by installing the corresponding trigger 40 into a single state. Connection takes place in setup mode. In the operation mode at the same time, the number of sensors involved in recognition is. which recorded the counter 12 number of sensors.

The addressing of the ROM 39 cells is as follows.

The cell address is fed to the address input of the block 39 from the output of the corresponding subtraction block 41.2,., 41, k, which determines the difference between the value of the received address and a constant number X. The X value for each subsequent ROM of the k-th sensor pair is determined by the formula ; X (k-1) p, where k is the number of a pair of sensors, p is the maximum number of steps of one pair of sensorsJ with p const, for all i 1 ... k. The input of the subtraction blocks 41 information comes from the corresponding elements 42 OR, the first inputs of which in the setting mode receive signals from the counter 3 addresses. In the operation mode, the address goes to the second input of the corresponding element OR 42 from the output of the calculating unit, and the address goes to the corresponding ROM 39 of all working sensors.

Such an organizing ROM 11 simplifies the setup and operation of the device1810

Unit 4 of the source code memory operates as follows.

At the first stage of tuning with the help of the toggle switch 30, the memory block 4 is set to the recording mode. The data inputs of all K blocks 29.1 ... 29.k are combined, to the input 3 of the data block enters through the element 31 OR information from block 7.

To the address input of 1 rows through element 32 OR information from counter 3 arrives. To address input of 2 columns through element 33 OR information arrives from counter 5 of the address.

To the input 2 of the sample of the decoder 6 and the inputs of the 2 elements 37 And the toggle switch 38 is logic O, when a output appears from the decoder 6 of the logical O, the signal is inverted at the input of the element 34 SH-NOT and through the corresponding element 34. block 29.- According to signals from the first pair of sensors, codes for the parts are formed (the number of which determines the number of lines in RAM 29) in the first block 29.1.

When the second pair of sensors is turned on, the codes of the blocks 29.2 continue to be formed, and the numbering of the addresses is controlled by the subtraction blocks 35.2 .., 35.k in the same way as the addressing ROM. In the setup mode on the second and t „d. In stages, the memory block 4 is set to read mode by the toggle switch 30. From block 2 and block 14, the formation of addresses by the gate 3 and counter 5 is set. First, the first line is addressed to block 21 of the code comparison, then all others are output and compared with each other.

The output to the output of the block is carried out through the element 36 OR. In the third configuration step, the columns are output from the memory block 4 in the same way as the rows are output. In the fourth stage, the settings for the input of the decoder 22 and the second inputs of the elements 37.1 ... 37, k are applied to the inhibitory potential of 1 toggle switch 38. At all the outputs of the decoder 22, logical 1 appears. 37 And logical O is fed to the inputs of a sample of all RAM 29. Block 14 sets the count of the number of steps to 1, address the first columns of all blocks 29, the information from all blocks 29 is parallel

I l1

but is output from block 4 and fed to sampling control block 15. In the setup mode, when repeating the third, fourth and fifth stages to the address input of the lines through the element

32IL Information comes from block 17 of the memory of part numbers, and to the address input of the columns through the element

33IL - from the memory block 16.

The sampling control unit operates as follows.

The selection of a specific block 56, block 58 and counter 66 is carried out by the corresponding element 50 I, the signal at the output of which appears with the coincidence of single signals generated by the decoder 51 and the decoder 52, and the switch 53 connects to the input of the decoder 52 in the setup mode the output memory block 4, and in the operation mode - the output of the sensor block 7.

The memory block of part numbers works as follows.

The block contains the number of blocks 57.1 .. 57, t, equal to the number of sensor steps remaining after the exclusion of non-informative positions. The number of blocks 58 ka healthy step grows 2 times. The data inputs through the element 59 OR information either comes from counter 3 or from the output of the address of block 18. The address inputs of the rows of blocks 63 are combined. The information comes from block 2. The select and write inputs of each block 58 are connected.

If there is a signal from block 15, the part number is written to the addressed line; if there is no TSR, block 58 is in read mode,

 The information from the blocks 58 through the element OR 60 passes to the output of the memory block 19.

The formation block 18 operates as follows.

The inputs of block 18 receive signals from the output of block 15. Each input corresponds to the counter 61 of the number of parts recorded in this block 58 The state of the counter 61 through element 62 OR goes to the decoder 63. The decoder 63 generates a signal only when the contents of the counter equal to 1, This signal sets trigger one to 64. The output of trigger 64 determines the information at the data output of block 17

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and at the output of register 65. In register 65, the address of the digit on the part number is written in a constructive way. So that the recording of the attribute was not carried out at the recording of the first part, since then the second, etc., can be recorded. the part, the decoder 63 is gated with delay element 67,

The delay element receives signals from block 15 through element 66 OR. The delay time is longer than the time required to record the next part.

Unit 19 display of the part number works as follows.

The part number is displayed in the process of operation from memory block 17 as a word. The last bit of the word — a sign — is applied to element 68 I, to another input of which a logical 1 is applied structurally through resistor 69. If the sign is 1, then the input from the output of register 70 of the part number receives a signal from the output of element 68 AND, which also goes to the blanking input of the decoder 71 controlling the indicator 72 and the part number is displayed on the indicator. In the course of operation, the register 70 records the number of the part to which the access occurred. The information about the part number enters the data input of register 70 from the output of memory block 17 and is written to register 70 by a signal from OR element 73, the inputs of which receive signals from the output of block 15.

Calculation unit 20 operates as follows.

Using this block, the number of the next step (optimal) for each working sensor is determined. Let the i-th step selected RAM 53 in block 16, in which the addresses of the optimum positions of the sensors are written. The first inputs of the subtraction blocks 74 are constructively assigned the number of sensor steps using the button 75, with the number at the first input increasing by each subsequent block 74 by p using the adders 84. The information from the block 16 enters the second inputs of the subtracting blocks The construction of information comes from the decoder 77, which passes information through the element 76 corresponding to this sensor. For

131

The first sensor block 74 subtraction is not used. The results of the subtraction through the OR element 78 arrive at block 79 in comparison with the number p and to the data input of the corresponding register 80. The signal Less than or equal from the output of element 79 is a signal that through the element 81 AND and the trigger 82 allows recording the next position of the corresponding sensor .

The trigger 82 and the element 81 also control the writing to the register 80 of only one given sensor. The trigger setup signal 82 is fed to the input of the corresponding delay element 83. The delay for the subsequent register increases. When all the registers 80 are full, the outputs of the delay elements 83 receive a signal from the registers.

The invention makes it possible to reduce the number of sensors to one pair (radiator-receiver) in comparison with the prototype, simplify the data processing during recognition and reduce the laboriousness of determining the position of sensors

Claims (6)

1. A device for recognizing: and accounting for parts moved by a conveyor (a fan containing a parts availability sensor, a first memory block, the first output of which is connected to the first input of the comparison unit, the first and second counters, the second memory block whose output is connected with the input of a digital-to-analog conversion unit, the output of which is connected to the input of the sensor actuator unit, kinematically connected with the sensor unit, the first decoder, the output of which is connected by a counter unit, characterized in that, in order to increase the reliability, avan and parts accounting, the third and fourth memory blocks, control blocks, signal shaping unit, calculating unit, third and fourth counters, second and third decoder and display unit, the output of the part number sensor are connected to the input of the first control unit, the first output of which through the first counter is connected to the first inputs of the first and even five 0 five Q Q s 1814 memory blocks, the output of which is the first output of the device. VA and connected to the second input of the first memory unit, to the first input of the display unit and to the input of the first decoder, the second output of the first control unit is connected to the first input of the second control unit, the second input of which is connected to the output of the sensor actuator unit, and the output to the inputs the second counter, to the second input of the comparison unit and through the fourth counter connected in series, the third counter and the third decoder to the first input of the second memory block, the second input of which is connected to the output of the calculation block, the second output The first memory unit is connected to the first input of the third control unit, the first output of the comparison unit is the second output of the device, the second output of the comparison unit is the third output of the device and is connected to the first input of the third memory unit, the second input of which is combined with the second input of the fourth memory unit and connected to the third output of the first control unit, the output of the second counter is connected to the first input of the third decoder, to the third inputs of the first, second and third memory blocks, the quarter of which input connected to the output of the third control unit, which is connected via the signal conditioning unit to the third and fourth inputs of the fourth memory unit, the fifth input of which and the second input of the indicator unit are combined and connected to the output of the third control unit, the second input of which is connected to the output of the sensors and the third to the output of the calculating unit, the output of the third memory block is connected to the input of the calculating unit and to the fourth input of the first memory block, the fifth input of which is connected to the output of the sensor block, the sixth the input is connected to the output of the third decoder, the second input of which is connected to the third output of the first memory block. 2. The device according to claim 1, characterized in that the first control unit contains a pulse generator, elements AND and OR, a counter and a start button, which is connected to the first input of the element OR, the second the input of which is the first input of the control unit, the output of the OR element is connected to the first input of the AND element, the second input of which is connected to the output of the pulse generator, and the output is connected to the counter input and is the first output of the first control unit, the output of the OR element is the second the output of the first control unit, the output of the counter is the third output 10 of the decoder, the elements AND, OR, the totalizer-first control unit, the subtractors, the element of comparison and 3. The device according to claim 1. about tl and address channels, kaledy of which is made on the element And, the delay element, trigger and register, output This is because the second control unit contains a trigger, a pulse generator, a start button ,. Element J5 of which is the output of the block. And. OR OR, the output of the second element of the number, the first inputs of the elements AND and OR, is the output of the second control unit, the first and second inputs of which are respectively 20 the trigger input and the inputs of the first OR element, whose code is connected to the first input of the first AND element, the second input of which is connected to the trigger output, the output to the first input of the second OR element, the second input of which is connected to the output of the second AND element, the first input of which The go is connected to the output of the pulse generator, the second input is connected to the start button. 4. A device according to claim 1, characterized in that the third control unit comprises a switch, decoders and elements, the outputs of which are the outputs of the third control unit, the outputs of the first decoder are connected to the first inputs of the elements AND, the second inputs of which are connected to the outputs of the second decoder The input of which is connected to the output of the switch, the input of which and the input of the first decoder are respectively the first, second and third inputs of the third control unit. 5. The device according to Claim 1, which means that the signal-shaping block contains counters, OR elements, delay element, register and serially connected decoder and trigger, the output of which is the first output of the signal-shaping block, output the register is the second output of the signal conditioning unit, the inputs of the counter and the second element OR are combined and are the input of the signal conditioner, the output of the second element OR the input of the decoder is combined and is the input of the calculation unit, the outputs of the decoder are connected to the second inputs of the AND elements, the outputs of which, starting from the second, are connected to the first input of the corresponding subtractor, the outputs of which are connected to the first group of inputs of the OR element, 25 whose second input is connected to the output of the first element I, and the output to the first input of the comparison element, the output of which is connected to the first input of the element I, in each address Channel 30 of each element I is connected to the first input of the trigger, the output of which is connected to the first input of the register and through the delay element connected to the second input of the trigger 35 and the second input of the register, the output of the first element I is connected to the second input of the element I and the third input of the first address register channel, the start button is connected to the second input of the reference element, with the second input of the first subtractor, with the first and second inputs of the first adder and with the first inputs of the remaining adders, the second input of each adder 45 and a second connected to the output of the previous adder, each adder output is connected to the secondary poi-fy entry corresponding subtractor, the subtractor outputs each soe50 .dineny to a second input of the second AND element a and the third input of the subsequent register address channel, 7, The device according to claim 1, wherein the comparison unit contains elements I, Iini, a comparison element, a register, a start button and a switch, the outputs of which are connected to the first inputs of the element the delay element is connected to the gate input of the decoder, the counter outputs through the first OR element are connected to the information input of the decoder, the trigger output is connected to the register input. 6. The device according to claim 1, characterized in that the calculation unit contains a start button. address channels, kaladyi of which is made on the element And, the element of delay, trigger and register, output which is the output of the block. the calculation, the first inputs of the elements AND and the input of the decoder is combined and is the input of the calculation unit, the outputs of the decoder are connected to the second inputs of the AND elements, the outputs of which, starting from the second, are connected to the first input of the corresponding subtractor, the outputs of which are connected to the first group of inputs of the OR element, the second input of which is connected to the output of the first element AND, and the output to the first input of the comparison element, the output of which is connected to the first input of the AND element, in each address the channel of each element And is connected to the first input of the trigger, the output of which is connected to the first input of the register and through the delay element is connected to the second input of the trigger and the second input of the register, the output of the first element And is connected to the second input of the element And, and the third input of the register of the first address channel, the start button is connected with the second input of the comparison element, with the second input of the first subtractor, with the first and second inputs of the first adder and with the first inputs of the remaining adders, the second input of each adder, starting at orogo connected to the output of the previous adder, each adder output is connected to the secondary poi-fy entry corresponding subtractor, the subtractor outputs of each soy .dineny to a second input of the second AND gate and a third input of the subsequent register address channel, 7, The device according to claim 1, such that the comparison unit acquires the elements AND, Iinii, the element of equilibrium, the register, the start button, the switch, the outputs of which are connected to the first inputs of the element This start button is connected to the first input of the OR element, the second input of which and the first input of the comparison element are combined and are the first input of the comparison unit, the outputs of the AND and OR elements through the register 130051818 The dinene with the second input of the comparison element, the outputs of which are respectively the first and second outputs of the comparison gate, the second inputs of the AND elements are the second input of the block, the comparison. Vsh2 Yb / xj FIG. g Fig.Z FIG. Fi.g.5 0m 3 dm 18 From 22 From 18 Wholesale 571 S 5 FY2.6 F "/ 7 4r.W Bw. Fig.8 fe I1 - Rtyon  cp 9 Put.te From -KSCHK L77 " From r ft Editor N.Gorvat (tgg Compiled by N.Vaga-nova Tehred I.Popovich Order 1152/50 Circulation 673 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 Proofreader A. Obruchar