SU1348823A1 - Device for shifting sequential numbers in redundant code - Google Patents

Abstract

The invention relates to computing and can be used in the construction of storage units. I, shift and normalization in systems operating with floating point and redundant number systems. The aim of the invention is to enhance the functionality by performing normalization. This goal is achieved by the fact that the device for shifting consecutive numbers in the redundant code, consisting of bit cells 2, each of which contains a register 3, elements AND 5, 10, element OR 7, counter 8 and trigger 9, introduces the element OR - NOT 6, element 11 and 11, and each bit of cell 2 contains a converter 4 from the auxiliary encoding to the basic encoding. 2 Il. (L

Description

The invention relates to computing and can be used in the construction of storage units, shear and normalization in systems operating with a floating point, and in redundant reading systems.

The aim of the invention is to enhance the functionality by performing normalization.

FIG. 1 shows a device for shifting consecutive numbers in a redundant code; in fig. 2 shows a scheme for converting a number from auxiliary encoding to basic encoding.

The device (Fig. 1) contains information input 1 of the device, bit cells 2, each of which

a vertical redundant numeral system in which three binary bits are assigned to represent any digit (-2 1.10, -1 -1.11, O 0.00, 1 f-O.OI, 2 0.10, 3 .ll). Therefore, cells 2 use three-bit registers and information input / output, there is a group 0 of their 3 inputs / outputs. The normalization mode is to exclude zero high bits. Zap is fixed before the most senior bit. Signed yes no. 15 The sign is determined by the sign of the highest

numbers. For example, the number (, 1.11 0.11 0.10), c (0, T 3 2 (-0.002).

Normalization is carried out by applying the potential to input 16. Moreover, it contains register 3 and converter 20 normalization is performed on both 4 numbers from the auxiliary coding by numbers stored in the device, as well as to the main coding, element II 5, element ШЖ-НЕ 6, element OR 7 , counter 8, trigger 9, elements AND 10, 11, input 12 of the device shift magnitude 25, inputs 13-16 of the shift, read, set, normalize device modes, clock input 17 and device output 18.

Converter 4 is a number from auxiliary 30 one-bit. Indeed, as a good coding into a basic code, a number in a redundant system (Fig. 2) contains the numbering element after performing any

operations are generated in coding (-2, -1, O, 1, 2, 3). During normalization, it is necessary to translate the number into the basic coding, since the execution of some operations, such as division, calculation of the reciprocal, must be carried out in auxiliary coding. Then, if the highest digits are maximal digits, then a transfer necessarily occurs from them. For example, - 33231 1, OOTTl (a bar over the digit means 45 that the digit is given with a minus sign).

and above the newly recorded. Both in the first and second cases, the normalization proceeds almost equally.

Consider the first case.

The recorded number takes n-1 times - p d, the senior n-bit is free. This is necessary with the intention that the normalized number can be increased by

AND-OR 19-23 and implements the following boolean expressions; Keny:

 n: hGh

., V p-p; x

about - t - - 4t

V p XX i 2 J

 .

-t-l

vn;

x x vn; npxjvn

 P

+1 -

3 V P,

n, x, v, x ;.

The conversion to basic coding is performed by recording the number with converters and cells 2.

  VП, X, X 2 VИ X,

--I- -1

  P, X ,.

The device works as follows.

In the storage mode, the control signals are missing and information is stored in the registers of the 3 cells 2. The device is designed to work with the fourth normalization by applying the potential to the input 16. Moreover, the normalization is performed both on the numbers stored in the device

and above the newly recorded. Both in the first and second cases, the normalization proceeds almost equally.

Consider the first case.

The recorded number takes n-1 times - p d, the senior n-bit is free. This is necessary with the intention that the normalized number can be increased by

0

five

The conversion to basic coding is performed by recording the number with converters and cells 2.

Consider this stage in more detail. Numbers are written to the device, starting with the higher bits. The first cell transfer inputs are connected to zero. The highest bit, in our case 3, is written to register 3 of the first cell 2. This number goes to converter 4, where it is converted to

a two-digit number, 11. The senior time + 1 series goes to the output of the transfer P.

and the youngest - on the information output of the cell (, 11, i.e. x

in the third cell 1, so P, coming to the input

x 1).

In the next clock cycle, 3 is again recorded in the first cell 2, -1 in the second cell. what about transfer

Converter 4 of the second cell 2, immediately goes to its information output. Thus, in the second cycle, 1 T 3 is recorded in the device. At the output of the first cell 2, the number 1 1 is formed. Transfer P 1, the input of the transducer 4 of the second cell 2 receives 1 from the register output 3 and 1 from the transfer input. At the output of the transducer 4, the second cell 2 is formed 00, and the output of the third cell 2 forms the number 01. Consequently, in the third cycle, 1012 is recorded in the device. There is no transfer. In the fourth cycle we have 10T23. The transfer arises from the second and third cells 2. As a result, in the fifth clock cycle, 100111 is recorded in the device, since the number is five-fold, the recording stops. Normalization begins. The signal at input 16 is equal to one. Therefore, the output of the element OR 7 clocking signal can be fed to the input cells. However, due to the fact that a significant bit is formed at the output 18, a zero signal is generated at the output of the OR-NOT 6 element and the clock series is not supplied to the cells. If there were zeros in the higher bits, the series would arrive until a significant bit was encountered. The number and normalization records actually coincide in meaning, therefore the recording and normalization modes are combined.

The reading is organized by applying a signal to input 14 and a clock series to input 17.

Shift mode This mode is intended to organize a delay in issuing a number relative to another. For this, from the input 12 into the counter 8, by the signal at the input 15, the number of bits for which it is necessary to delay the issue of the number is entered in the additional code. At the same time, trigger 9 is reset to zero. A signal is fed to the input 13 of the device and a clocking series. Counter 8 is working on clock pulses from input 17. When appearing through the number of clocks equal to the shift value,

0

0

The pulse overflow output trigger 9 is set to one, allowing the passage of clock signals through the elements AND 10, OR 7 and the clock inputs of the cells 2.

Claims (1)

Invention Formula A device for shifting consecutive numbers in a redundant code, containing n bit cells (n − 1 - the number of digits), each of which contains a register, two AND elements, 5, the OR element, the counter and the trigger, the information input of the device connected to the information input of the first bit cell register, the clock input of the device connected to the first inputs of the first and second elements AND, and the counting input of the counter, the information input of which is connected to the device shift input installation mode input 5 of which is connected to the input of the reception of the counter and to the zero input of the trigger, the single input and the output of which are connected respectively to the output of the counter and to the second input of the second element And, the third input of which and the second input of the first element And are connected respectively to the inputs of the shift and read modes of the device , the outputs of the first and second elements And are connected respectively to the first and second inputs of the OR element, the output of which is connected to the inputs of the resolution of the reception of registers of the right cells from the first to the nth, different m, that, from the whole extension of functionality due to the expansion of normalization, it contains the element OR NOT, the third element of each field cell - the number converter from the auxiliary coding to the basic coding, and the clock input and the input of the normalization mode are connected to the device -: with the first and second inputs of the third element AND, the third input and output of which are connected respectively with the output of the OR element and with the third input of the OR element, the output of the number converter from the auxiliary The main coding of the K-th bit cell is connected to the information input of the register (K + 1) -th bit cell five 0 five 0 (, ..., n-1) ,,, the outputs of the bits of the number converter from the auxiliary coding to the main coding of the n-th bit cell of the connection do not match the input element and 13488236 OR is NOT and is the output of the device, and in the bit cell the output of the register is connected to the input of the number converter from auxiliary encoding to the basic encoding. Editor N. Slobod Nick Compiled by V. Berezkin Tehred A. Kravchuk Proofreader E. King Order 5191/48 Circulation 670 Subscription VNIIPI State Committee of the USSR for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab. D. 4/5 Production and printing company, Uzhgorod, st. Project, 4