SU1302320A1 - Shift register - Google Patents

Abstract

The invention relates to the field of computer technology and can be eliminated for shifting binary codes that have at least two zeros to the right of each unit. Such codes include, for example, codes with irrational openings: Fibonacci p-codes and golden p-proportion codes, moreover, p2 -2. The aim of the invention is to simplify the device. In the shift register, one-step / 5-flip-flops are used, and the shift is performed in two cycles. In the first cycle, the unit is rewritten from the previous trigger to the next one, and in the second cycle, the forward trigger is set to zero. Unlike the prototype, the shift register contains an inverter and has other connections between adjacent bits. 1 il. 1 tab. "(L with about to with to about

Description

The invention relates to computing and can be used to shift operational codes in which to the right of each unit there should be at least two zeros (codes with irrational bases: Fibonacci p codes and golden p-codes, and).

The aim of the invention is to simplify the shift register.

The drawing shows a diagram of a shift register containing, for example, 5 bits.

Each register bit contains / 5-trigger, first and second elements I.

The diagram shows / 5-trigger 1-5, the first 6-10 and the second 11-15 elements And, the inverter 16, the first 17 and second 18 clock inputs, information input 19 and information outputs 20 of the shift register.

The shift register works as follows.

Suppose code 010010 arrives at input 19 ... Pre-triggers I-5 are set to zero (setting chains to zero are not shown). The code is recorded and shifted in two clocks: the first beat is the beat of the unit, the second beat is the beat of the zero record. The clock signals arrive at inputs 17 and 18. Suppose that the first (0) digit of the input code is valid on the input 19. When the signal is fed to input 17 (in a nerve cycle), the state of the flip-flops 1-5 does not change.

In the second cycle, input zero is signaled to input 18, while triggers 1-5 also remain in their previous states.

Upon delivery to the input 19 of the second bit (1), a single signal is generated in the nerve clock at the output of the element 6, under the action of which the trigger 1 is set to one, resulting in the output of the element 7 7

Initial installation of OO

Unit Record

Write zeros

Unit Record

Write zeros

Unit Record

Write zeros

O1 unit record

Write zero1

Units Record11

Record zerosI, C

trigger 2 is also set to one. Triggers 3-5 remain as they were. In the second cycle, input zero is sent to input 18, and a single signal is generated at output 11 of element 11, and trigger 1 is set to the zero state, while triggers 2-5 remain in the same state.

When applying to the input 19 of the third bit of the code (0) and to the input 17 of the enable signal of the recording of units, the trigger 3 is set to one, the remaining triggers remain in the same state. In the second cycle, input zero is sent to input 18, under which a trigger 2 is set to the zero state, while the remaining triggers remain in their previous states.

When a code (0) is fed to the input 19 of the fourth section and to the input 17 of the enable signal for writing units, the trigger 4 is set to one. The remaining triggers remain as they were. In the second cycle, input zero is sent to input 18, under which a trigger 3 is set to the zero state. The remaining triggers remain as they were.

When a code (1) is fed to the input of the 19th of the second bit and to the input 17 of the signal of the resolution of the record of units, the trigger 5, as well as the triggers 1 and 2, are set to one. Triggers 3-4 remain as they were. In the second cycle, input zero is signaled to input 18, under which triggers 4 and 1 are set to the zero state. The remaining triggers remain in a clean condition, and so on.

The table illustrates the operation of the register.

Thus, the code entered into the register is fixed on the second-to-fifth-point triggers, and the first register bit performs auxiliary functions.

Claims (1)

Invention Formula The shift register containing in each bit de / 5-trigger and the first and second elements And, the outputs of which are connected to the S- and / -inputs / 5-flip-flop, respectively, the first input of the first element And each bit is the first clock input of the register, the second input of the first element of the first bit is the information input of the register, and the outputs of the 5-flip-flops of each bit, except the first, are information outputs of the register, characterized in that, in order to simplify the register, it contains an inverter whose input connected to the second input of the first emitter AND of the first bit, the first input of the second element AND of each bit is the second clock input of the register, the second input of the first element AND of each bit, except the first, is connected to the single output / 5-flip-flop the previous bit, the third input of the first element of the / / th digit,, n, n is the number of register bits, connected to the zero output of the / 5-flip-flop ((-2) -th bit, the third input of the second element And the second bit is connected to the output of the inverter, the second input of the second element And each bit, except for Lednov, coupled with a single output / 5 latch subsequent discharge, and the second input of the second AND element is connected to the last discharge with zero output / 5-latch previous discharge.