SU1310806A1 - Device for shifting information - Google Patents

Abstract

The invention relates to computing and can be used in computer processors. The aim of the invention is to reduce the volume of equipment. The goal is achieved by the fact that a device containing a group of multiplexers 1, working register 2, output register 3, counter 4, decoder 5, first element NOT 6, elements 8 and 13c of the first through sixth and first element of the IP 16, contains the second element 7, the seventh and eighth elements And 14, 15 and the second element OR 1 7 with the corresponding connections; 1, silt, 2 tab. cl

Description

The invention relates to computing and can be used in computer processors,

The purpose of the invention is to reduce the amount of equipment.

The drawing shows a diagram of the device for shifting information.

The device for shifting information contains a group of multiplexers 1, a working register 2, an output register 3, a counter 4, a decoder 5, the first 6 and the second 7 elements HE, the first 8,. second 9, third 10, fourth II, fifth 12, sixth 13, seventh 14 and eighth 15 elements AND, first 16 and second 17 elements OR, device clock input 18, device start input 19, device shift code input 20, device 21 device shift directions, device information input 22 and device output 23.

The device dp shift information works as follows.

The device performs shift operations in eight clock cycles. In the first cycle, information is received in the output register 3. Dn next 000

XXXXX

XXXXX

about x x x x

five

0

five

Modified data (shifted or transformed using multiplexers 1 depending on the magnitude and direction of the shift) is written to register 2.

In the initial state (there is no signal at input 19), the input information from input 22 through multiplexers 1 with control code 000 at the output of counter 4 is written to register 2 by the single value of the signal at input 18. When a single signal appears at input 19, the initial information is written to the output register 3 and the counter 4 is modified. The operation signal: the device is generated by a clock inversion and is present for all eight clock cycles.

Input 20 defines a five-digit binary shift code, and input 21 indicates the direction of the motor (one value is right shift, zero value is left shift).

In tab. Figure 1 shows the generation of a controlled information recording signal in register 3.

Table I

1 1 Record Background Information

1 1 Cross code.

1 o Storage of information

1 o Storage of information

XX X1

Xxxx

XX XX

XX XX

NOTE. LI, L2, ..., L16 - left shift by I, 2, ...,

bits;

X is an indifferent state. 25

Depending on the state of the output of the element OR 16 in the output register 3, information is modified or stored.

The operation of multiplexers 1 (for each bit of the multiplexer), for i-ro bits (from 1 to 32), the table is defined. 2

Table 2

thirty

After the execution of eight, the signal from input 1 is removed, the signal of the signal into register 3, i.e. the result of the shift is saved in p and arrives at exit 23.

Claims (1)

Formula invented A device for shifting and containing a work register register, a group of multiplexed counter, deffrarator, first OR, the first element is NOT and AND, and the bits of the device’s input with the first information inputs of the multiplexer outputs are connected to the corresponding bits of the 45 input of the worker the register, the running time of which is connected with the current bits of the information of the input of the output register, in which the output of the clock input is connected to the counting input of the counter, the input device is connected to the input element NOT, the input is The resolution of the output register is connected by the output of the first element AND whose input is connected to the first element OR of you, whose first, third, fourth, and pins of which are connected respectively Continuation of table 1 X X X 1 about 1Shift L 8 0 Storage 1Shift L 16 I Perekr. code, O Storage of information sixteen general state. 25 thirty After eight clock cycles, the signal from input 19 is removed and the write signal to register 3 is blocked, i.e. the result of the shift operation is stored in the register and goes to output 23. Invention Formula 0 five five 0 A device for shifting information containing a working register, an output register, a group of multiplexers, a counter, a deprecator, the first element OR, the first element is NOT and six elements AND, the bits of the information input of the device connected to the first information inputs of the corresponding multiplexers of the group, the outputs of which are connected to the corresponding bits of the information 5 input of the working register, the bits of the output of which are connected to the corresponding bits of the information input of the output register, the output of which is the output of the device, the clock input of which is connected to the counting input of the counter; The third, fourth and fifth inputs of which are connected respectively to the outputs of the second, third, fourth, fifth and sixth elements And, the first output of the decoder is connected to the first input of the second element And, characterized in that in order to reduce the volume of equipment, it contains the second element NOT, the second element OR, the seventh and eighth elements AND, with the clock input of the device connected to the enable input of the working register and, through the second element NOT to the second input of the first element AND, the output bits the counter is connected respectively to the inputs of the decoder, the outputs of which from the second to the eighth are connected respectively to the first input of the second element OR, the first input of the fourth element AND, the first input of the fifth element AND, the first input of the sixth element nta And, the first input of the seventh element And, the first input of the eighth element And, and with the second input of the second element OR, the output of which is connected to the first input of the third element And, exit1 and 7 of the seventh and eighth elements And connected to the sixth Compiler A, Klyuev Editor E. Kopcha Tekhred L. Oleinik Proofreader L. Order 1892/45 Circulation 673 Lodpnoe VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab, 4/5 Production and printing company, Uzhgorod, st. Project, 4 108066 the seventh inputs of the first element OR, the bits of the input of the shift code of the device are connected respectively to the second inputs of the fourth, fifth, 5 of the sixth, seventh and eighth elements And, the second inputs of the second and third elements And are connected respectively to the device start input and the device shift direction input, the output of the first element is NOT connected to the meter installation input, the output bits of which are connected respectively to the control inputs group multiplexers, second 15 the information input of the i-ro multiplexer of the group (i 1-32) is connected to the (33-i) -M output bit of the output register, (k + 3) -th information input of the p-th multiplexer of the group (k 20 0-4, p 1- (32-2) is connected to the (p + 2) th output of the output register, (k + 3) -th information input of the m-th group multiplexer (m (32-2) + 1-32) is connected with exit 25 of the first element NOT, the eighth information input of the i-ro multiplexer of the group is connected to the (33-1) th output of the output register.