SU1352627A1 - Multiphase clock generator - Google Patents

Abstract

The invention relates to a pulse technique and can be used as a multiphase clock generator in various nodes and devices of computing equipment, control and regulation tools. The purpose of the invention is to expand the functionality of the device, achieved by providing programming of the pulse period on the output tires of the device and simultaneously inhibiting the appearance of pulses on a given group of buses of the higher channels of the device. The goal is achieved by introducing into the device two m4) iggers 19 and 26, two elements AND 6 and 21, element OR 9, element OR-NOT 33, and element 7 delay. The device also contains a control bus 1, a resolution bus 2, a parallel bus 3, a code, an initial installation bus 4, a bus 5 clock pulses, registers 8 and 16, a decoder 11, a second group of elements AND 12-15, the first group of elements AND 22-25 , output clock bus 27, output bus channels 28-31, and input gate bus 32. When asynchronously controlling a sequence of 1 pulses, bus 1 is used. Bus 32 has a pulse with an adjustable duty cycle and a period, 1 slug. (L 00 ate yu

Description

The invention relates to a pulse technique and can be used as a multi-phase clock generator in various nodes and devices of computer technology, control and regulation means.

The aim of the invention is to expand the functionality of the device by ensuring the programming of the pulse period on the output buses of the device and the simultaneous prohibition of the occurrence of pulses on a given group of buses of the older channels of the device.

The drawing shows a block diagram of the device.

The multi-phase clock generator contains control bus 1, resolution bus 2, parallel code bus 3, initial installation bus 4, bus 5 t of pulse pulses, second element AND 6, delay element 7, first register 8, element OR 9, first terminal 10 decoder 11, the second group of elements And 12-15, the second register 16, consisting of T7-20 triggers, the first element And 21, the first group of elements I. 22-25., the second trigger 26, the output clocking bus 27, weekend / Bus channels 28-31, output gate bus 32, the element OR NOT 33.

The information inputs of the register 8 are connected to the buses 3 parallel code, and the outputs are connected to the inputs of the decoder 11, the bus 5 clock pulses connected to the clock input of the register 16, the first inputs of the elements 21-25 and the input of the delay element 7, the output of which is connected to the trigger input of the trigger 10 ,, information and the reset input of which is connected to bus 4 of the initial installation 4, and the output is connected to the reset inputs of registers 8 and 16 and the first input of the OR element 9, the output of which is connected to the single input of the trigger 26 whose output is connected to the bus e 32, and the second input is connected to the element ID 22 and. The output elements AND 22-25 are connected to the shinai 28-31, and the second inputs are connected to the outputs of the register 16 and the inputs of the element OR-NOT 33, whose input is connected to the second input of the element And 21 and the first input element And 12, the third input of which is connected to bus 1, the outputs of the decoder 11 are connected to the second inputs

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elements AND 12-15, the outputs of which are connected to the information inputs of the register 16, the outputs of the flip-flops 17-19 which are connected to the first inputs of the elements AND 13-15, respectively, the output of the element 21 and 21 connected to the bus 27 and the second inputs of the element OR 9 and the element 6 , the first input of which is connected to bus 2, and the output is connected to the clock input of register 8.

The device works as follows.

The group of elements 12-15 and register 16 form a special type of shift register, in which the rewriting of data from the i-th bit into (1 + 1) -and bit depends on the control signals from the decoder outputs 11. The write data into each trigger of register 16 is performed on a decay (falling edge) of clock pulses.

The parallel input of the decoder has P bits. Between the number 5 bits P. and the number of register triggers 16 (M) has the following relationship: M: 2. Moreover, the outputs of the decoder 11 with numbers larger than M do not engage with.

To ensure the programming of the pulse period on the output buses of the device channels and the simultaneous prohibition of the occurrence of pulses on the group of buses of the device's upper output channels, the output of each i-ro trigger (1 i M) is connected to one of the inputs (i + 1) -ro element And groups items and 12-15. Another input of each element And a group of elements And 12-15 is connected to the same (element And) output of the decoder 11, It. allows you to block the spread of a high level signal through a chain of register triggers from a specific trigger due to the presence of a low level signal only on one of the outputs of the decoder 11, depending on the parallel code supplied to the input of the decoder 11c of the output 8.

Thus, the control of the pulse period on the output buses 28-31 of the device is carried out by breaking the logical interrelation between the triggers of the register 16. At the same time, the occurrence of the pulses on the older channels j through M-th is blocked, if j is interrupted and proportional

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the pulse period on the output tires from first to (j-l) -ra is reduced.

Parallel P-bit register 8 is designed to store a parallel code defining the pulse period on the output buses of the device. The code is written into register 8 at the edge of the signal at the output of the AND 6 element.

The trigger 10 is designed to provide a reliable initial turn on of the device after power is applied, eliminating the appearance of a transient process at its outputs.

After turning on the power, the signal on the device control bus 1 is high, the signal on

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Not 2 resolutions are low, 20 first inputs of elements And, in parallel code 3, the required code is given, the signal on the initial setting bus 4 is low, and clock pulses are sent to the clock pulse bar 5. In this case, the pulses are generated only on the output clock line 27, since the signal at the inverse output of the trigger 10 has a high level. This blocks the operation of registers 8 and 16 and RS flip-flop 26.

After sending the high | level signals to the initial setup

4 with a delay of time due to the delay element 7, the D-flip-flop 10 is set by the pulse decay, while the registers 8 and 16 of the flip-flop 26 are enabled. After the high-level signal is applied to the resolution bus 2, the pulses coming from the output of the And 21 through the element AND 6 to the clock input of the register 8. A code 8 is written on the pulse front at the output of the element AND 6, the register 8.

In this case, pulses are formed on certain output channels of the device channels. To change the period of the following pulses, a new code is fed to the bus 3, and then a signal is sent to the bus 2 of the resolution. On the front of the pulse at the output of the AND 6 element, a new code is written into the register 8.

Asynchronous pulse train control uses control bus 1. Submission of a low-level signal to this bus blocks the signal on all output buses 28-31 after the first group, whose outputs are connected to the output buses of the corresponding channels, and the second inputs are connected to the outputs of the same bits of the second register, which are to the last , are also connected to the first inputs of the subsequent elements of the second group, which are different in that, in order to expand the 30 functionality, two negations are introduced into the neg, two elements of the OR element, the OR-NOT element, and a delay element whose input is It is connected to the clock pulse bus, and the output is connected to the clock input of the first trigger, the information and cus input of which is connected to the bus of the beginning installation, and the output is connected to the reset inputs of the registers and the first input of the OR element whose output is connected to the zero input of the second trigger the output of which is connected to the output gate bus, and the single input is connected to the output of the first element AND of the first group, the first input of which is connected to the first input of the first element I, the second input of which is connected to the first input of the first And the second element of the second group and the output of the element OR NOT, the inputs of which are connected to the outputs of the second register; information inputs of which are connected to the outputs of like elements of the second group, the second inputs of which are connected to the corresponding outputs of the decoder, and the third input of the first element of the second group is connected to the control bus, while the resolution bus is sub40

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52627 i

Vanilla pulse on the last, from unblocked channels.

An output pulse having an adjustable duty cycle and a period is formed on the output gate bus 32, and the low signal level informs about the possibility of asynchronous change of the signal follow-up period on the output buses 28-31.

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Claims (1)

Invention Formula Multiphase clock, j. containing the first register, the information inputs of which are connected to the bus and parallel code, and the outputs are connected to the inputs of the decoder, the second register, the clock input of which is connected to the bus clock pulse5 five 0 first inputs of elements AND the first group, the outputs of which are connected to the output buses of the corresponding channels, and the second inputs are connected to the outputs of the same bits of the second register, which, besides the last, are also connected to the first inputs of the subsequent elements AND of the second group, characterized in that 0 functionality, two triggers are entered into it, two AND elements, an OR element, an OR-NOT element, and a delay element, whose input is connected to the clock pulse bus, and the output is connected to the clock input of the first trigger, information the first and reset input of which is connected to the bus of the initial installation, and the output is connected to the register reset inputs and the first input of the OR element, the output of which is connected to the zero input of the second trigger, the output of which is connected to the output gate bus, and the single input is connected to the output The first element AND of the first group, the first input of which is connected to the first input of the first element AND, the second input of which is connected to the first input of the first element AND of the second group and the output of the OR-NOT element, whose inputs are connected to the outputs of the second register; information inputs of which are connected to the outputs of like elements of the second group, the second inputs of which are connected to the corresponding outputs of the decoder, and the third input of the first element of the second group is connected to the control bus, while the resolution bus is sub0 five 0 five ment And, the output of which is connected to the clock input of the first register, and do of the OR element, at the first input of the AND element and the output clocking bus, Editor L.Povkhan Compiled by V. Potapov Tehred M. Khodanych Order 5575/55 Circulation 900 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 Proofreader A. Obruchar