SU1339900A1 - Device for checking uniformly weighted code - Google Patents

Abstract

This invention relates to automation and computing. Its use in digital information processing systems simplifies the device. The device contains a shift register 1, groups 3, 4 of the AND elements and an encoder 6. The introduction of the former 2 blocking signals and the element 5 OR does NOT allow the memory register contained in the prototype to be abandoned, which leads to a simplification of the device. 1 hp f-ly, 2 ill. U with so with so

Description

113399002

The invention relates to automation. The device operates as follows computer technology and may be.

used in processing systems In the initial state register 1

digital information, reset from input 9, to recording input

The purpose of the invention is to simplify the shift register 1 is supplied by the resolution of the device. The potential (signal) and in register 1

Fig. 1 shows the functional code of the input code from inputs 7.

on the circuit of the device for control Upon termination of the signals at input 9 on

equilibrium code; 2 shows an example of a Qtakt input 8, which are clocked.

perform one bit of registration pulses. When applying the clock shift .pulse there is a code shift by one

Device for controlling equilibrium discharge to the right (towards the first time

code contains register 1 shift. p yes). At the moment of time when the discharge of 1.1-l.n, shaper 2 igr 1.1, turns out the blocking signals, the first and second codes (the ONE potential for pr 3 and 4 elements And, the output element of discharge 1.1), with

OR-NOT 5, encoder 6, informational inverse output blocking turns 7, clock and control inputs of transfer signals to bit 1.1.

8 and 9, the first and second outputs 10 and 11, 20 With further receipt of the clock

Shaper 2 signals of blocking pulses state of discharge 1.1 ki is performed on the elements OR 12. It can be changed independently of signals on the form n-1 to its transfer inputs 19. When the OR transitions, the output of the i-ro element of the RShI is unit state of bit 1.2 is reconnected to the () th output of the block, and the 25th shift of the zero output signal - inputs - to the block inputs from the first output on the second output of the forcer 2 to ( 1 + 1) The first output block soy-blocking signals. It arrives at the dinine with the first input, the i-th input of the blocking input 18 of the 1.2 block, and when k is connected to the inverse output, the next receipt of the clock 1-bit 1.1 register of the 1 shift register. Zopulsov state of the discharge 1.2 is not the form factor 2 signals are blocked. The operation of the device of the origin can be performed in the form of a n-1dit in this way, until the moment when the OR elements combined in a single state will be divided. The output of the 1st element OR of the connection is 1.1-1.t of the shift register 1 and is inn with the (1 + 1) -th output of the block. The inputs “zero” are bits 1. (t + 1) -1.n, where t is the j-ro element of the IL of the first group is the soy-number of units of the input code. In this dinene with the inputs of the block from the first point at the outputs of all elements And (j + 1) -ro. The inputs of the j-ro element of the OR group 4 are present zero potential of the K-th group (K 2, ..., p) connectors, which causes a single potential output of the last element OR 40 of the output of the element AND NOT 5, swi (K- 1) -th group and with inputs of the block otdel- tvuyuschuyuschiy about the end of the cycle pa- ((/ + 2) -th to ((/ + j + 1) -ro, where -o / is the number of the device's loops. At the same time, the unit OR elements in the groups 1- (К-1). Potential is present only on each digit of register 1 shift of one t-ro element AND group 3

can be performed (figure 2) on the trigger, by entering the inputs of the encoder 6,

pax 13 and elements 14. Calls at exit 10 a code for the number t

In Fig.2 marked information, by: module K.

clock and control inputs 15–17 The operation cycle of the device is over, bit 1.1, blocking input 18, input of which indicates a single transfer path 19, direct and inverse potential at the output of the element OR NOT 5. outputs 20 and 21. Thus, the introduction of the blocking signal generator 2 allows

When performing the digitizer 6 on the electronic memory register is deleted, than the possessions OR their inputs are connected to the inputs of the device simplification, dami encoder 6, while the inputs of the 1st

Claims (2)

of the RShI element are connected to the jth inputs of the Formula about the acquisition of the encoder 6 in such a way that in the 1st The resolution of the representation of the number j is by mo-1. A device for controlling the indignod K contains a one-digit code containing an n-bit which are connected to the corresponding inputs of the OR-NOT element, the direct bits of the shift register are connected to the second inputs of the first and second groups of the same name, the first group and the first group and the output of the n-th shift register are connected to the corresponding input of the encoder, the output element OR NOT the shift register, the inverse outputs of the bits of which from the second to the nth are connected to the first inputs of the elements AND of the first group from the first to (n-1) -th, the encoder and the second group of n-1 elements AND, information, clock and control the inputs of the shift register are the corresponding inputs of the device, the outputs of the encoder are corresponding to the first outputs set by the second output of the device, the device, characterized in that, to simplify the device, the nth element is entered into it And the second group, the element OR NOT, the former locking, the inputs of which-J5 that are connected to the inverse outputs of the simultaneous bits of the shift register, the outputs of the blocking signal generator are connected to the blocking inputs of the same bits of the shift register 20 and the first inputs of the same name elements of the second group, the outputs 2. The device according to claim 1, so that the blocking signal generator is made on n elements OR, the output of each of the ryhs, except the last, is connected to the first input of the next, first input of the first element OR connected to the first input and output, the form, the second input and output of each element OR are the corresponding inputs and outputs of the imaging unit. Editor O. Yurkovetska Order 4351/56 Circulation 901 VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 which are connected to the corresponding inputs of the element OR NOT, the direct outputs of the bits of the shift register are connected to the second inputs of the same elements of the first and second groups, the outputs of the elements of the first group and the direct output of the n-th bit of the shift register are connected to the corresponding inputs of the encoder , the output element OR NOT Is the second output of the device Is the second output of the device 2. The device according to claim 1, that is, that the driver of the blocking signals is made on p-1 elements OR, the output of each of which, except the last, is connected to the first input of the next, first input the first element OR is connected to the first input and output of the former; the second input and output of each element OR are the corresponding inputs and outputs of the former. x, - fuz.Z Compiled by O. Revinsky Tehred M. Hodannch Subscription