SU1126953A1 - Control device - Google Patents

Abstract

A CONTROL DEVICE containing a memory block and two registers, the first and second groups of outputs of the memory block are connected respectively to groups of information inputs of the first and second registers j whose clock inputs are connected to the clock input of the device, the reset input of the first register is connected to the device reset input . the group of outputs of the first register is connected to the group of high address bits of the memory block, the group of outputs of the second register is the first group of outputs of the device, characterized in that, in order to reduce the amount of equipment, the device contains a trigger, a multiplexer and an element NOT, and the control inputs the multiplexer is connected to the group of outputs of the first register, the clock input of the device through the element is NOT connected to the clock input of the trigger, the 1-input of which is connected to the output of the multiplexer, whose information inputs are a group of the code input device, a third group of outputs, block C r memory is the second group unit outputs a trigger output connected to a lower address discharge block memory. HS 01

Description

The invention relates to automatics, computing and computing, and can be used in digital automation devices. A firmware control device is known that contains OR elements, groups of AND elements, memory blocks, registers, a pulse generator, and a delay element ClJ. The disadvantage of the known device is a large amount of equipment. The closest to the present invention is a control device containing a semiconductor permanent storage device (GSHZU), the first and second groups of outputs of which are connected to the r-inputs of the first and second B-registers with dynamic. Contacting C-inputs connected to the input a clock bus, input bus conditions, an input bus reset, connected to the I input of the first B, register, whose codes are connected to the inputs of the higher bits of the PROM address, and outputs of the second B register connected to the synchronous output buses control signals, the input clock bus is connected to the blocking potential input of the fixture circuit, D-INPUTS of which are connected to the input condition busses, the outputs of the fixation circuit are connected to the inputs of the SHZU address digits, and the input bus is reset to f the input of the second B-register. This device has a rather simple structure and is applicable for the implementation of a wide class of FZJ digital automatics devices. The disadvantages of this device are the large hardware costs, due to the significant amount of EPROM (introducing every input condition requires doubling the amount of EPROM), the complexity of programming (associated with expanding the EPROM) and the impossibility of implementing asynchronous output control signals with an arbitrary change in the input conditions ( in this service the output signals of the PROM are not deterministic). The layer of introduction of a sufficiently large number of input conditions and the absence of asynchronous output control signals significantly limit the functionality of a durable device. 1 The purpose of the invention is to reduce the amount of equipment. This goal is achieved by the fact that the control unit containing a memory monitor and two registers, the first and second groups of outputs of the memory block are connected respectively to groups of information inputs of the first and second registers, the clock inputs of which are connected to the clock input of the device, the reset input of the first the register is connected to the reset input of the device; the group of outputs of the first register is connected to the group of higher address bits of the memory block; the group of outputs of the second register is the first group of outputs of the device va, introduced trigger ,, multiplexer and NOT element, wherein the control inputs of the multiplexer are connected to grutspoy BL moves the first register, a clock input device NOT soedr1nen through the element. with clock trigger input. The D input is connected to the output of a multiplexer, the information inputs of which are a group of code inputs of the device, a third group of inputs of the memory block is the second group of outputs of the device, the output of the trigger is connected to the lower address bit of the memory block. FIG. 1 shows a block diagram of the device. The device contains reset input 1, code input groups 2, clock input 3, multiplexer 4, element NO 5 trigger 6, memory block 7, registers 8 and 9 of output groups 10 and 11. The device operates as follows. The device (as a digital automaton) has 2 stable states - ver, tires, where h is the width of the first B-register 8. The setting signal,. arriving at the reset input 1 sets the B-register 8 to the initial zero state. Subsequently, the states of the D-register 8 are changed by the clock signals received via the clock bus 3 to the C input of the D register 8 in accordance with the operation algorithm of the control device. FIG. 2 shows an example of a graph operation algorithm. On the graph, a control unit is implemented for 16 states of vertex states from O to F (a lister of a decimal code), which corresponds to a four-bit register 8, and fourteen states (from O to I) are functional as well. two sos then (s) F - redundant. The graph algorithm inside the vertex circles shows the numbering of the WQ-WP states (states of the register 8), the corresponding internal states checked by the external conditions Xp-XP (the signals on the tires of conditions 2) in the forward or inverse form, arrows are marked transitions. In addition, the operator vertices in which synchronous (C, C, Cj, C and / or asynchronous) are excited (with (-I 2 3 output control signals supplied to outputs 10 and 11 are marked with corresponding symbols. In this case, considered a variant of four synchronous (register 9 - four bits) and four asynchronous output control signals. In the proposed control device, no number of restrictions is imposed on the numbering of the graph vertices (the numbering of the vertices is arbitrary), with the exception of the zero vertex of the initial state WQ, into which the It is reset by input 1. From each current state of the vertex (depending on the state of the corresponding selected input bus conditions), a clock is transmitted in one of two possible successive states, with the following transitions possible: both subsequent states They are different from each other and differ from the current state (on the graph below. The current states W, 2 Nos) are vertices of two conditional transitions -. one of the following states repeats the current state, and the second subsequent state is different from it (current states VQ, H „Wgj) - the vertices of waiting for the transition conditions; both subsequent states are identical between themselves and differ from each other from the current state (current states Vj, fj, W, Wg EDD) - vertices of unconditional transitions; both subsequent states are identical to the current state (current state of WQ) - dead-end vertices, of which the transition to another state is possible only by a reset signal. Thus, the proposed managerial device implements all possible sequential algorithmic transitions, and each state is assigned an individual input condition that comes from a group of inputs 2. In addition, each of the vertices can be an operator one, i.e. Arrays can be excited by arbitrary sets of synchronous and / or asynchronous: output control signals, respectively, to groups of outputs 10 and 11. The change in the states of the device and the generation of output control signals occurs as follows. Input 3 receives external negative polarity clocks. The code signals of the current state from the outputs of register 8 are sent to the control inputs of multiplexer 4, which transmits to the D input of the p-trigger 6 the state of one of the inputs 2 corresponding to the text SOSTYAN1PO. Simultaneously} but the code of the current state is sent to the higher bits of the block 7 address, and the lower bit of the block 7 address receives the output trigger signal 6. In the pauses between the clock signals of the B trigger state 6, registers 8 and 9 are fixed, and From the outputs of register 9 and from the third group of outputs of block 7, outputs 10 and 11 receive, respectively, synchronous (C – C) and asynchronous (ot), output control, signals. On the leading (negative) front of the next clock signal coming through the NOT 5 element at the C input of the trigger 6, the latter fixes the condition code at the input 2 selected by the multiplexer 4 according to the current status code. The current status code of register 8 and the new status code of trigger 6 form the address of block 7, which, on the first and second groups of outputs of block 7, form the codes of subsequent states of registers 8 and 9, respectively, arriving at B-inputs of the ETT-OS registers . On the back (positive) edge of the clock signal, going to the C inputs of registers 8 and 9, the subsequent state code and the synchronous output signal code corresponding to the 1.11xh of this state are fixed in the latter. Simultaneously with a third group of outputs of the 7, an asynchronous output code is generated the signal corresponds to the fixed state of the register 8 "Next, the state remains unchanged until the next clock signal arrives.

Since block 7 is binary addressing, then each of the 2 device states corresponds to 2 pairs of output words of block 7 (addressing by older bits), and an alternative choice of the right word, from word t; are determined by the state of trigger b (addressing the least significant bit) block 7)

Programming block 7 on the graphal algorithm is quite simple.

Fig. „3“ represents the programming table, block 7 of the exemplary graph-algorithm 1 of the operation of the control device,

Here, the code of the address of block 7 is represented by the hexadecimal address of the four most-significant bits A (code of the current state of the register 8) and. the binary address of the junior pkzr yes A, (the code of the current condition X is on the lth information input 2 multiplex 4, which is in trigger 6) „

The code of the first group of outputs of block 7 (the code of the last state of register 8) is represented in hexadecimal code. Codes second and third

Output groups of block 7 are represented by bit in binary codes - respectively, synchronous columns (C 5 C, 3 C, C C) and asynchronous

5 (, 9 2, 3 ° 4 output control JOIItHX signals.

Asynchronous output control signals come from the second group of outputs of block 7 to outputs 11 directly, therefore, the coding of the columns & 1, is done according to the graph algorithm on the column W. current state Since the sets of output control signals are determined by 5 liters of the device only by the internal state of the device and do not depend on the external conditions, their values are entered in the table by identical pairs B with two rows of alternative values X. for each vX-. The duration of the gaps in asynchronous output control signals occurring on the fronts of the clock signals does not exceed the delay of the block 7

5 (if necessary, cuts are easily eliminated by subsequent strokes - .vL-ieM or by integration)

Synchronous control signal: dog, from the second group of outputs

G block 7 to outputs 1,0 through a clocked register 9 with a delay per clock, therefore, the encoding of columns C - € 4 is performed in accordance with the graphalgorithm on the column W after the end of airtix with this:

fa.2

Claims (1)

A control device comprising a memory block and two registers, the first and second groups of outputs of the memory block being connected respectively to the information input groups of the first and second registers, the clock inputs of which are connected to the device clock input, the first register reset input is connected to the device reset input, the group of outputs the first register is connected to the group of senior address bits of the memory block, the group of outputs of the second register is the first group of outputs of the device, characterized in that, in order to reduce of the equipment, the device contains a trigger, a multiplexer and an element NOT, moreover, the control inputs of the multiplexer are connected to the group of outputs of the first register, the clock input of the device through the element is NOT connected to the clock input of the trigger, the D-input of which is connected to the output of the multiplexer, the information inputs of which are a group code inputs of the device, the third group of outputs. the memory block is the second group of outputs of the device, the trigger output is connected to the lowest address bit of the memory block. SU _W) 1126953 J ________________________ Figure 1>