SU1242963A1 - Device for checking address buses of interface - Google Patents

Abstract

The invention relates to automat. tick and computing and,. can be used to control some functions of the interface. The device monitors the address buses of the interface. In order to increase the reliability of control, the device contains n analysis blocks, where n is the address bus width of the interface. Each analysis block contains a decoder, an encoder, a modulo three convolution scheme that provides a modulo three residue from the input address. In case of coincidence of this module with control iodine, the subscriber corresponding to this address is switched on; in case of a mismatch, the analysis unit is disconnected from the interface buses. 3 il. W

Description

one

The invention relates to computing and can be used to control the operation of the interfaces of processors, microprogram machines or other systems.

The purpose of the invention is to increase the reliability of the control.

FIG. 1 shows the block diagram of the proposed device; in fig. 2 - encoder scheme; in fig. 3 is a diagram of a threshold unit.

The device contains -controlled interface 1, p blocks 2.1-2.p analysis, information outputs 3.1-Z.p, decoders 4.-4, p, encoders 5.1-5.p, nodes 6.1-6.P convolution modulo P, schemes 7.1.-7.p comparison, elements OR 8.1-8.P, bus- 9 settings of the control module, encoder Yu, register 11, display unit 12, reset input 13, element OR 14, element group AND 15, element 16 , threshold block 17, element AND 18, generator 19 clock pulses, counter 20, decoder 21, element OR 22, group of elements OR 23, switch group 24.1-24.p, output 25 sbo, decoder 26 and elements 27 of the indicator - ii.

The encoder (Fig. 2) contains adders 28 modulo two.

The threshold block (Fig. 3) contains the elements And 29 and the element OR 30.

The encoder 10 (Fig. 2) performs the summation in the Hamming subset according to the following formulas:

So - + a, + a - “; S, ...; S b + P, 4-p. + a. + ...

where 1 5 i b in this case is equal to

to zero.

a, ... a - information bits, their values are determined by the signals taken from the outputs of the Unequal circuits 7.1.-7.P comparison; + - mathematical sign

summation over any two.

Based on these formulas, an IO encoder is constructed for the three control circuits.

.

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. -sumum S, 3 and S b subsets of Hamming.

The threshold unit 17 controls the presence of a signal at the output

5 schemes 7.1-7. P comparison of blocks 2.1-2.P analysis. If a signal is received from only one comparison circuit 7, there is no signal at the output of the threshold block 17. No signal

10 and then, when no signal is received from any of the comparison circuit 7. In case more than one signal is received on the encoder 10 (i.e., two, three and t-d.), Then from the output of the threshold, 15 of the block 17, a signal equivalent to a logical unit is output, which with the help of the HE element 16 prohibits the passage of information through the element and 15 ..

20 The number of analysis units is determined by the number of interface bus addresses. Sa (i.e., the number of subscribers) o Such devices, such as operational, memory

25 device, etc.

Switch 24 operates as follows.

If a signal equivalent to a logical one is received at the output

The 30 elements OR 23, the switch 2.4 is closed, thereby removing power from all the elements of the blocks 2, .p analysis.

The miiHe address receives information about the address of the selected subscriber. The aboyment is connected to the outputs 3.1-3, n of the device. .

The reference module modulation bus 9 receives a modular reference balance, which is determined depending on the address number (the weight of the address word code)

The device works in the following way.

From interface 1, the address code appears at time t and goes to decoder 4. From its output, information goes to encoder 5, and from there to convolution node 6 modulo p. The latter minimizes the information received modulo p and determines the remainder. From the output of this node, the remainder goes to the first group of inputs of the comparison circuit 7. To the second group of inputs of this circuit: the reference residue is fed from the bus 9 of the task of the control module. Synchronization mode comparison implemented 40

 .

on the signal, coming from the input of the element OR 8, If the information coming to the first and second groups of inputs of the comparison circuit 7 coincides, then from the input Equal to the circuit, a signal equivalent to the logical one is output. Nota at the appropriate address.

If the information supplied to the first and second groups of inputs of the comparison circuit 7 does not match only in one of the analysis blocks 2, then the output of the unequal comparison circuit 7 removes the output signal, which is sent to the encoder 10, where, in accordance with the described law, the folding of information and its recording through the elements I 15 into the register 1 I.

Information from the output of register 11 goes through the element OR 14 to the output of the device and to the display unit, where the fault location is determined by the decoder 26. .

If interference occurs (i.e., signals of the type of the unit constant) on the address buses of interface 1, it is triggered. to the choice of two or more subscribers, or in the event of faults in two or more decoders 4, signals are output from two or more comparison circuits 7. In this case, the threshold unit 17 is triggered, which gives a signal to the element NOT 16, prohibiting the passage of information through the elements 15 and 15, as well as the input of the element 18, preparing it for opening. On the other input of the element {18 the pulses come from the generator of 19 clock pulses. A counter is recorded in counter 20. From the counter 20, a code combination is fed to the information inputs of the decoder 21. For example, the decoder 21 excites one of the output buses, which provides a signal through the OR 22 and 14 elements to the output of the device. Simultaneously, from the first output of deynfrater 21, the signal goes to switch 24.1, which removes power from the first block 2.1 of analysis.

By commands from the decoder 21, both one and several analysis units can be switched off, i.e. subscribers do not turn on for non15

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The same address from the outputs 3.1-Z.p device. .

The capacity of the counter 20 and the decoder 21 is selected based on the number of 5 subscribers (addresses) /

The information from the decoder 21, i.e. information on those analysis units from which power has been removed is fed to the display unit 12.

ten

In case if any analysis block 2 is disconnected using block 2.1 as an example and when the next address taken from the interface 1 address bus appears, the input of the encoder 10 comes from only one comparison circuit 7, then from the threshold block 17, a signal equivalent to logical zero is output. This makes it possible to pass information from the cipher. The rator 10 through the elements 15 and to the input of the register 11. From the output of the register 11, the information goes to the decoder 26, which transfers to the block 12

25 cation information about the faulty unit 2 analysis.

Thus, the display unit 12 receives information from the decoder 21 about the disabled analysis unit (subscriber) or group of subscribers and register 11 of the failed analysis unit, which allows you to extract the erroneous address of the interface that was being addressed to the subscriber.

The reduction to the original (zero) co

5, the stand-up of register 11 and counter 20 is performed by a reset command, arriving at the input 13 of the device.

20

thirty

40

Formula of Invention

A device for monitoring the address bus interface containing a clock pulse generator, a group of elements I. the first element OR, the decoder,

45 register, the element NOT, the element And, the counter, and the outputs of the counter are connected to the information inputs of the decoder, the information inputs of the register are connected to the information inputs

50 decoder, the information inputs of the register are connected to the outputs of elements AND groups, the group of outputs of the register is connected to the group of inputs of the first element OR, different

55 by the fact that, in order to increase the reliability of the control, it contains n analysis blocks (where n is the number of controlled address buses of the interface), an encoder,

the second element OR, the threshold block, n switches, a group of elements OR the display unit, and each i-th analysis block (i 1, ... n) contains a decoder, an encoder, a convolution node modulo p, a comparison circuit and the element OR, in each i-th analysis block, the information inputs of the decoder are connected to address control ports of the monitored interface, the outputs of the decoder are connected to the information inputs of the encoder and the inputs of the OR element, the output group of the output generator is connected to the first group of information outputs of the comparison circuit The second group of informational inputs of which is connected to the bus of the control module of the device, the resolution input of the comparison circuit is connected to the output of the OR element, the outputs are unequal comparison circuits of all analysis blocks are connected to the information inputs of the encoder and the threshold block, the output of which is connected to the first the input element And through the element is NOT with the first inputs of the elements And the group, the second inputs of which are connected to the outputs of the encoder, the output of the clock generator is connected to the second input

element And, the output of which is connected to the counting input of the counter, the reset input of which is connected to the device reset input and the register reset input, the decoder outputs from the first to the nth are connected to the first inputs - the OR elements of the group and the nth inputs of the second element OR , (n + 1) -th output of the decoder is connected to the second inputs of the OR elements of the group and (n + 1) -m input of the second OR element, the output of which is connected to the input of the first OR element, the output of which is the code of the device; Decoder outputs from the first to (n + 1) -th are connected to the first group of information inputs of the indication module; the second group of information inputs are connected to the register register group; the outputs of the OR elements are connected to the control inputs of the corresponding switches; the information inputs are connected to the device power bus, the outputs of the group switches are connected to the power inputs of the corresponding blocks a; The results of the comparison circuits of all analysis units are with the information outputs of the device.

FIG. 2

| 3J

Compiled by A, Sirotska Editor O. Yurkovetska Tehred O. Gortvay Corrector A. Tsko

Order 3706/48

Circulation 671 Subscription VNIIPI USSR State Committee

for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5

Production sholigraphic enterprise, Uzhgorod, st. Project, 4

 m

/ 7

fig.Z

Claims (1)

Claim A device for monitoring the interface address buses, containing a clock generator, a group of elements I. the first element ^ OR, decoder, 45 register, element NOT, element AND, counter, moreover, the outputs of the counter are connected to the information inputs of the decoder, the information inputs of the register are connected to information inputs 50 decoders, the information inputs of the register are connected to the outputs of the elements AND groups, the group of outputs of the register is co? unified with the group of inputs of the first OR element, characterized in that in order to increase the reliability of control, it contains η analysis units (where η is the number of monitored address buses of the interface), an encoder, a second OR element, a threshold block, η switches, a group of elements OR, an indication block, and each ϊth analysis block (i = 1, .., η) contains a decoder, an encoder, a convolution unit modulo p, a comparison circuit, and an OR element, and in each i-th analysis block, information inputs of the decoder connected to the address buses of the controlled interface 10, in moves decoder connected to the data inputs of the encoder and the element inputs or outputs through the band coder. a convolution unit modulo p is connected 15 to the first group of information outputs of the comparison circuit, the second group of information inputs of which are connected to the control job bus. device module, the input of resolution 20 of the comparison circuit is connected to the output of the OR element, the outputs of the comparison circuits of all analysis blocks are connected to the information inputs of the encoder and the threshold block, the output of which is connected to the first input of the AND element and through the element NOT to the first inputs of the AND elements groups whose second inputs are connected to the encoder outputs, the output of the clock generator • is connected to the second input of the AND element, the output of which is connected to the counter input of the counter, the reset input of which is connected to the reset input the device and the input of the register reset, the decoder outputs from the first to the ηth are connected to the first inputs of the OR elements of the group and the ηth inputs of the second OR element, the (n + 1) -th decoder output is connected to the second inputs of the OR elements of the group and (n + 1) th · the input of the second OR element, the output of which is connected to the input of the first 'OR element, the output of which is the device failure output, while the outputs of the decoder from the first to (n + 1) th are connected to the first group of information inputs of the indicator block the second group of information inputs of which is connected with a group of register outputs, the outputs of the OR elements of the group are connected to the control inputs of the corresponding switches, the information inputs of which are connected to the power bus of the device, the outputs of the group switches are connected to the power inputs of the corresponding analysis units, go to fig1