SU962959A1 - Adaptive redundancy system - Google Patents

Description

The invention relates to computing and can be used in redundant control systems, as well as in adaptive redundant devices with increased reliability.

A device for controlling the operational Ps1mti is known, which contains a modulation convolution circuit. These are two, a memory data register with check bits triggers, a comparator unit, a convolution by MODE. GPO, a control bits-fl conversion unit.

However, this device does not fully utilize the modular control and control capabilities of the comparison, in particular, errors of any multiplicity that may arise in the information read from the RAM block are not detected promptly (for example, control by the MODU. is a multiplicity error of two).

A data processing system with triple units is also known, comprising triple units of data processing, connected by means of triple standard connections to memory units. A computer: a rator with a majority body is connected to each three-fold connection of the system unit for monitoring information, so that at each moment it evaluates data obtained from two standard connections 23.

The disadvantage of the system is a loss of performance in the presence of multiple errors in the information flows of two memory blocks, since

10, the comparators do not allow for the prompt determination of a serviceable third block in the presence of two failed ones, which reduces the reliability of this sistell.

The closest technical

15 of the essence of the invention is an adaptive redundant device containing multi-bit comparison circuits, some of the inputs that are connected to the outputs of the restoring organ, and others to the outputs of the corresponding redundant channels, b. adaptations whose information inputs are connected to the corresponding outputs of the reserved

The 25 channels, the control inputs, with the outputs of the comparison circuits, and the information outputs, with the inputs of the restoring orgay and the failure indicators of the reserve / normal channels (the failure triggers). in addition, it contains a trigger and

thirty

the output element OR, whose inputs are connected with the signal outputs of the adaptation blocks, and the output with the counting input of a trigger, zero output, which is connected to the first, and the single OUTPUT - with the second signal inputs of the adaptation blocks, each of which contains four elements And, trigger imitations O and 1, the element OR NOT and the element OR, the output of which is connected to the information output of the adaptation unit, one input - with the output of the fourth element AND, the first input of which is connected to the information by the input of the adaptation unit, and - with zero output three ger simulation O unit input simulating a trigger 1 is connected to the output of the second AND gate having a first input connected to a first signal input of the adaptation unit, and a single simulation input trigger O. connected to the output of the third element And, the first input of which is connected to the second signal input of the adaptation unit, and the second input of the second and third elements And connected to the output of the first element And the signal output of the adaptation block, the first input of the first element And connected to the first signal input of the block Adaption, the second input is with the input of the failure indicator and the output of the OR-NOT element, one input of which is connected to the single output of the simulation trigger 1 and the second input of the OR element, and the second input with the single output of the trigger and itatsii 0 t3J. .

The disadvantage of the device is that it provides non-operative control of multi-bit information in case of failures of different multiplicity in two channels, and, consequently, adjustment for the remaining serviceable third channel, which reduces the system's efficiency and its reliability.

The purpose of the invention is to increase the reliability of the device.

The goal is achieved by the fact that an adaptive redundant device containing in each channel a multi-bit comparison unit, whose inputs are connected to the information outputs pe3epBHpyeNbJX of nodes of the same name and subsequent channels, and an adaptation block, the treasury of which contains a decoder of the control code connected by the outputs to the control outputs of the channel, three AND elements, the first OR element and fault indicators, in home channel comprises a second OR gate, and each adaptation block - fixing interrupt trigger element 2I-J-OR

The first and second major elements, the element NAND, the element NOT and the four elements OR, and in the adaptation block for each channel the first and second inputs of the first element AND are connected to the outputs of the second element OR of the first and third channels, the first and second inputs of the second element AND - to the outputs of the second element OR of the second and first channels, and the first

0 and the second inputs of the third element AND - to the outputs of the second elements OR of the third and second channels, the third inputs of the first, second and third elements AND are connected to the output

5 of the first element OR, the first input of which is connected to the input of the element NOT and to the output of the element NAND, whose inputs are connected to the outputs of the second element OR of all channels, youQ is NOT connected to the first input of element 2I-OR, and the second input of the first element -OR connected to the inverse output of the second major element and to the second and third inputs of the element 2И-OR, the outputs of the first, second and third element AND are connected to the first inputs of the third, fourth and fifth respectively of the elements OR and to the inputs of the sixth element IL Whose output

0 is connected to the fourth input of element 2И-OR, the second input of the third element OR is connected to the output of the control unit modulo two first channels, the second inputs of the fourth and fifth

5 elements OR to Block Outputs

control modulo two of the second and third channels, respectively, the outputs of the three control modules modulo two are connected to the departures of the second major element of the adaptation block of a given channel, in which the outputs of the third, fourth and fifth OR elements are connected to the inputs of the corresponding fault indicators, the outputs of which connected to the inputs of the control code decoder and to the inputs of the first major element, the output of which is connected to the fifth input of the element 2И-OR, connected by the output to the input of the interrupt latch trigger, the stroke of which is connected to the interrupting output of the switch, and the inputs of the second OR element of each channel are connected to the outputs of the multiple bits of the comparison unit of the given channel.

5 i The drawing shows a diagram of the device.

The proposed device contains a redundant node 1, unit 2 control modulo two, multi-bit

0 comparison block 3, second, OR element 4, adaptation block 5, failure indicators, interrupt latch trigger 7, OR elements, 9 2И-OR element, first 10 and second 11

5 major elements, a decoder 12 control codes, elements AND element 14 AND-NOT, element 15 NOT, information lines 16, interrupting outputs 17, control outputs 18 and elements 19 and 20 OR. The device works as follows. In the initial position, the trigger 7 and the indicators 6-6 j are in the zero state, in node 1 there are no malfunctions and therefore information is compared over all bits at the inputs of blocks 3 at the inputs of the interfan. Comparison and code control of unit 5 is set to zero (signals from elements 4 OR and from blocks 2. At interrupt output 17 from; there is no signal to interrupt the computational process, and at outputs 18 there is a code corresponding to the majority mode of receiving information from trunk 16. In the process long-term operation in nodes 1 there are faults that lead to the occurrence of errors of different multiplicity in the information line 16. The first failure that occurs, for example, in node 1 of the first channel, is detected by a block 2, revealing the appearance of errors in the information that are not a multiple of 2. The same errors, but the multiplicity will always be detected by blocks 3. The principle of error detection and fixing is as follows. Suppose, for example, in the information of node 1 of the first channel errors in the zero, first and second bits. Then, as a result of bitwise comparison of the information of its own and subsequent channels, at the inputs of the interchannel equation of blocks 5 there is a code 101, corresponding to the code on the output of 1x 4 OR elements of the first, second and third channels. The indicated code 101 is fed to the inputs of elements 14 AND-NOT and 13 I. At this, the enabling signal 1 at the input of the element NOT 15 does not change from its position and at the output of the element 13, a signal 1 appears, which, through the element 8 (OR, sets the indicator 6 to one, which corresponds to the failed node 1 of the first channel. Block 2 will fix this error. At the inputs of the code control of block 5, the code 100 with 1 is sent to the first failed node that passed through the element 8 OR, confirms the single state of the indicator 6. The remaining elements The first failure on node 1 of any channel can be fixed similarly. In cases of failure, on any node 1 On the trunk x 16 of the failed channels there can be various combinations of errors in the bits. Depending on the combination of errors, it is necessary to make appropriate decisions on their countering. All combinable errors in the information of nodes 1 of two channels can be classified according to the signs of the multiplicity of errors in nodes 1 of the channels and the relative position of errors between the bits of nodes 1 ka als. Let us consider the operation of the device for some typical failure situations. Option 1. At nodes 1 of the first and then the second channels, errors of odd multiplicity occur, the failed bits at nodes 1 overlap each other, but there is no full correspondence of the failed bits. In this case, at the inputs of the inter-channel comparison of block 5, the code 111 is present, corresponding to the code on the output of the 4 OR channels. This code in block 5 is fed to the input of element 14 AND-NOT and the zero signal at the output of element 19 OR prohibits the passage of this code to write to indicators 6-6. . At the inputs of the code control unit 5, code 110 appears, formed by unit 2, which, having passed through the elements 8 OR, sets indicator 6 to one and confirms the single state of indicator 6. At the same time, the specified code enters the inputs of element 11 and sets a zero signal at its output, which closes element 9 2I-OR and prohibits writing to the one state of the trigger 7. Thus, block 5 in this failure state determines the failure of nodes 1 and sets unit state corresponding indicators 6, unit signals from the outputs of which are fed to the inputs of the decoder 12 and output 18 shows the code for rebuilding the majority elements of the outer device to work from the healthy node 1 of the third channel. Option Q. At nodes 1 of the first and second channels, even multiplicity errors occur, the failed bits are superimposed on each other, and there is a full correspondence of the failed bits between the 1 channels. At the second inputs of block 5, there is a code 011, which is decoded by elements 13 AND and sets indicator 6 to one, which falsely indicates a malfunction of node 3 of the third channel. However, with a single indicator indicator 6, previously

set in one state, and indicator 6 to the input of element 10 receives code 101, which is looped down at the output of this element M. Code 1 appears at the output of element 8 by a signal from the output of element 13g and. The absence of a malfunction code of nodes 1 of the first and second channels from blocks 2 causes signal 1 to appear at the output of element 11. This triggers element 2I-OR and the trigger 7 is set to one, and output 17 appears interrupt signal of the computational process.

Thus, when the information of the nodes 1 of the error channels of even multiplicity appears, which are not detected by block 2, the device does not promptly receive the signal and erroneous information. A further search for a healthy node 1 is performed by software.

Option And. At nodes 1 of the first and second channels, an odd multiplicity error occurs, the failed bits overlap each other, and there is a full correspondence between the failed bits between the nodes 1 of the channels.

At the inputs of the code control unit 5, there is a code 110, which is fed to the inputs of element 11. The output of this element produces a zero signal, which through element 19 OR prohibits the passage of code 011 from the inputs of unit 5 through element 13 I. At the same time, code 110 passes through the elements 8-8 OR and sets the indicator 6, j to one, and also confirms the single, indicator state b. Further operation of the device is similar to option 1.

Consequently, the occurrence of odd multiplicity errors in the channel nodes 1 is hardware-determined by the device, and the majority element control code is promptly generated without interrupting the computational process.

The efficiency of the device is increased if, instead of the code control modulo two in block 2, another, more effective modular control is used, for example, modulo control 3,5,7 or modulo numerical control 15.

The proposed device improves reliability by quickly determining the moment of occurrence of shtsbok in the information and make the appropriate decision on the effect of the parrying effect. In addition, the device provides operability of an redundant redundant system in the event of errors of any multiplicity, when hardware control modulo two and interchannel control

by comparison, each individually, is unable to promptly fix an error and determine the remaining healthy channel. All this increases the reliability of information in the control system of an adaptive backup device.

Claims (3)

1. USSR author's certificate number 333559, c. 06 F 11/20, 1970. 2. The patent of France 2163284, kl.S 06 F 11/20, published. 1973. 3. The author's certificate of the USSR I 496560, c. 06 F 11/20, 1973.