SU1305870A1 - Device for converting numbers from positional number system to modular code - Google Patents

Description

inputs of the second OR element, which is associated with the control inputs of the group inhibit elements and the control input of the switch,

one

The invention relates to computing technology and can be used for interfacing computing devices operating in non-positioning number systems with positional computing devices, as well as in data communication means using modular codes.

The aim of the invention is to extend the functionality by converting a number into a two-stage modular code.

FIG. shows the functional diagram of the device; Fig. 2 is a block diagram of the formation of constants; in FIG. 3, time diagrams of the operation of the unit for forming constants for the case when the number of senior and junior modules is two.

The device for converting numbers from the positional number system to the modular code contains registers 1,2 and 3, switches 4 and 5, unit 6 converting the position code according to a given module and block 7 forming constants, input 8 of the device number being converted, input 9 Start device, output 0 End of device conversion, output 11 of the device result, input 12 and outputs 13-17 of the constant formation unit 7.

Block 7 (FIG. 2) of the formation of constants contains an OR 18 element, a delay element 19, counters 20 and 21, memory nodes 22 and 23, an SHSh 24 element, a group of prohibition elements 25, an OR 26 element group, and a switch 27.

As block 6, any known device for converting numbers from a positional number system to a system of residual classes in an arbitrary modulus can be chosen. The delay element 19 has a delay time of 5 T (t is the average time of transitional processes in each individual functional element

information input, :(, which is connected to the input of the first counter and through the delay element - to the second input of the first element OR.

devices, to simplify understanding of the principle of operation of the device, assume that all elements are the same. Counters 20 and 21 count from one to t + 1 and n, respectively.

Nodes 22 and 23 of the memory contain codes of the lower 10, P - P and higher (P - P) modules, respectively, in order of increasing.

The following principle of operation is used.

Convertible number A taken from

and the range of R P P is converted

i g 1

modulo P., i Ijn, referred to as the senior modulus, and after receiving each residual FL | P - it, in turn, is transformed modulo P

j 1, the one that is called junp

modules, such that

)

20 30

25

7 max | A | p. |, Resulting in npj was

i; 1

That is how a two-stage modular code of the number A is obtained, which can be written in the form of a two-dimensional

array, denoting

il,

|

// A / r. fp + through

,, ..., 2,

fin

L

ii - i- ni --- n.

When the proposed device is operated, the rows of the reduced matrix will be sequentially formed at its output.

A device for converting a number from a positional number system to a modular code works as follows.

In the initial state, registers 2 and 3 are zeroed, the converted number A is entered in register 1, the potential inputs at the control inputs of the switches are zero, the code of the first senior PV module is set to output 17, block 6 is ready

g

to convert the number A modulo P, the impulse arriving at the input 9 Start, passed through the element OR 18, allows the supply of clock pulses to block 6. (The input of the clock pulses is not shown in the drawing). When block 6 finishes converting the input pulse at input I2, it turns on the corresponding pulse, which will allow passing through switch 27 to output 14, recording the result of the conversion / A / p to register 3 after passing through switch 5.

At this time, the pulse received at input 12 in block 7 of formation of constants, will increase the contents of counter 20 by one, which will lead to the formation at the input of node 22 of the code of the first junior module P, which goes through the element OR 26 and

The output 17 to the information input of the block 25 occurs until it contains 6. Moreover, the code of the senior module, the clamping of the counter 21 does not increase before the output of the node 23, passes through the group of elements 25

Then the impulse, signifying the end of the last transformation, will pass through the input 12 to the input of the counter.

prohibition, since the control input will have a unit potential formed by the element OR 24 in the presence of any code at its outputs. The same potential will set switches 4.5 and 27 to the appropriate state, in particular, switch 4. connect the output of register 3 to the information input of block 6.

In case you need to convert the number A to the usual one

At the time determined by the delay element 19, after the arrival of a 40-step modular code, the necessary impulse is at input 12 (the delay time is 10

equal to the maximum time required to establish a new module at the information output of the constants forming unit 7) the same impulse, passed through the OR 18 element, will allow the delivery of clock pulses to the block 6. Conversion result

Connect devices to the output of counter 20, but not 21. The first major module, P, needs to be taken 45 such that its range of change is equal to the range of change of the convertible number. In this case, the number A will pass through block 6 without changing and in the next cycles of operation

0. through the switch 5, arrives at the input of the register 2. At the same time, 50 solutions will calculate all / A / Pj, the input of the resolution of register 2 will be

after which the conversion of the number will end, and a new number can be written to register 1.

a pulse is transmitted from input 12 through switch 27 to output 15,

which will allow the output code on the output 11 of the device In this way, all residues d, -; by

ten

first senior module. When., The contents of counter 20 will increase

to m + l, the next pulse at its input will cause a pulse at its output overflow, which will increase the contents of counter 21 by one, which will form at the output of node 23 the code of the next higher module that passes through the group of prohibition elements 25, since at the control input element 15 or 24 will be formed by zero potential, which will also set switches 4.5 to 27 to the appropriate position. This will happen because the counter 20 will be in a single state, 20 which corresponds to the zero code at the output of the node 22. Then all the residuals oij will be obtained: - after which the high module will be changed. Similarly, the conversion process will be

25 until the contents of counter 21 increase to

n. Then the impulse, signifying the end of the last transformation, passes through the input 12 to the input of the counter.

30 and will cause the appearance of a pulse at the overflow output of this counter, which will go to the input of counter 21 and will cause a pulse on its overflow output, which will go to the input

j 10 devices and can be used to write the new number to be converted to the input register,

In the event that it is necessary to convert the number A to the usual one-step modular code, the output 10 is necessary.

connect the devices to the overflow output of the counter 20, and not 21. The first major module, P, needs to be taken 45 such that its range of variation is equal to the range of variation of the number being converted. In this case, the number A will pass through block 6 without changing, and in the next cycles of operation of the device, all / A / Pj will be calculated,

all / A / Pj will be calculated,

after which the conversion of the number will end, and a new number can be written to register 1.

Claims (1)

DEVICE FOR CONVERTING NUMBERS FROM POSITIONAL NUMBERING SYSTEM TO MODULAR CODE, containing two registers, a unit for converting a positional code for a given module and a unit for generating constants containing a first memory node and a first counter, the bit output of the first counter connected to the address input of the first memory node, input the converted number of the device is connected to the input of the first register, the output of the second register is the output of the result of the device, characterized in that, in order to expand the functionality by converting a number into a two-stage modular code, it contains two switches, a third register, and the constant generation unit additionally contains two OR elements, a second counter, a group of OR elements, a group of inhibit elements, a group of OR elements, a group of inhibit elements, a delay element, the switch and the second memory node, and the outputs of the first and third registers are connected respectively to the first and second information inputs of the first switch, the output of which is connected to the information input of the conversion unit positioning code for a given module, the information output of which is connected to the information input of the second switch, the first and second outputs of which are connected respectively to the information inputs of the third and second registers, the device start input is connected to the first input of the first element OR of the constants forming unit, the output of the first element OR and outputs of elements * OR groups of which are connected respectively to the start input and to the input bit of the value of the module of the position code conversion unit an output module whose output is connected to the input of the first counter of the constant generation unit, the first and second outputs of the switch, the output of the second OR element, the switching output of the second counter of which are connected respectively to the input enable input of the third register, the input enable input of the second register, the control inputs of the first and the second switch, with the output The end of the conversion of the device, moreover, in the block forming the constants, the overflow output of the first counter is connected to the input of the second counter, discharge the output of which is connected to the address input of the second memory node, the bit output of which is connected to the information inputs of the group inhibit elements, the outputs of which are connected to the first inputs of the corresponding elements of the OR group, the second inputs of which are connected to the output bits of the first memory node and to the corresponding inputs of the second OR element, the output of which is connected to the control inputs of the group inhibit elements and to the control input of the switch, the information input of which is connected to the input of the first counter and through lement delay - to the second input of the first OR gate.