SU1151946A1 - Information input device - Google Patents

Abstract

DEVICE FOR INPUT OF INFORMATION, containing a block of comparators, digital-analog converter, first and second reversible counters, first OR element, first register, AND element, encoder, control unit, the first input of which is the second input of the device, second output of the control unit connected to the second input the first reversible counter, the third and fourth outputs of the control unit are connected to the first and second inputs of the second reversible counter, respectively; the third input of the control unit is connected to the output of the first About the OR element, the output of the D / A converter is connected to the input of the comparators block, the inputs of the second group of which and the inputs of the AND element are connected to the outputs of the first register, the output of the AND element connected to the second input of the control unit, the input of the encoder is the first input of the device, the inputs of the first group of the Comparators block are the inputs of a group of devices, characterized in that, in order to improve speed by organizing independent processes for converting information and its response to the request signals, it contains The second register, the second element OR, the multiplexer and the block of registers, the inputs of the second and third groups of which and the inputs of the first and second groups of the digital-to-analog converter are connected to the outputs of the first and second reversible counters, respectively, the outputs of the comparators block are connected to the inputs of the first register and the first element OR, the inputs the first groups of the second pe (L registrar and block of registers, outputs from: the first, second and third groups of which are connected to the inputs of the first, second and third groups of a multiplexer whose outputs are you With the first device group, the first output of the control unit is connected to the first inputs of the first reversible counter, the first and second registers, the outputs of the second register are connected to the inputs of the second element OR O) and the encoder, the codes of the first group of which are connected to the inputs of the second group of the second register The outputs of the second group of the encoder are connected to the inputs of the fourth group of the multiplexer and are the outputs of the second group of the device, the output of the second OR element is the output of the Device Request.

Description

I The invention relates to automation and computer technology and can be used in automatic cte fax control and monitoring. A device for inputting information is known, which contains comparators5 a digital-to-analog converter, a pulse maker, an encoder of a pulse generator, a counter5; key block ,, registers, interlock unit and delay element pj. The disadvantages of this device are the low speed and probability of a failed situation when two or more comparators are triggered at the same time. The device for input information; the maintenance block of the comparative toroV; digital-to-analog converter, first and second reversible counters, first element OR, first register element AND, encoder, control unit, the first input of which is the second input of the device, the second output of the control unit is connected to the second input of the first reversible counter 5, the third and fourth outputs of the unit Controls are connected to the first and second inputs of the second rechargeable counter, respectively; the third input of the control unit is connected to the code of the first element IL1-13 of the output of the digital-tax converter To the input of the comparator block, the inputs of the second group of which and the inputs of the And element are connected to the codes of the first register, the output of the And element is connected to the BTOpoj - sy input of the control unit, the input of the encoder is the first input of the device, the inputs of the first group of comparator block are the inputs of the device 2 group The drawbacks of the known device are the speed of the input losses caused by the loss of input time due to the need to read the reversible counters before overflow, and the inability to convert signals larger than voltage equivalent to the amount of bits of the first up-down counter. The purpose of the invention is to increase the speed of reaction by organizing information processes for converting information 46. , 2 mation and its results on the request signals. The goal is achieved by the fact that the device for inputting information contains a comparators block, a digital-analog converter, first and second reversible counters, the first OR element, the first register, the AND element, the encoder, the control unit, the first input of which is the second input of the device, the second output The gravity unit is connected to the second input of the first reversible counter, the third and fourth outputs of the control unit are connected to the first and second inputs of the second reversible counter, respectively, the third input of the unit The input is connected to the output of the first element OR, the output of the digital-to-analog converter is connected to the input of the comparators block, input; c 1 of the second group of which and the inputs of the And element are connected to the outputs of the first register, the output of the And element is connected to the second input of the control unit, the input of the encoder is the first input the devices, the inputs of the first group of the comparators block are the inputs of the device group, contains the second register, the second OR element, the multiplexor register block, the inputs of the second and third groups of which and the inputs of the first and second The D / A converter groups are connected to the outputs of the first and second reversible counters, respectively, the outputs of the comparators block are connected to the inputs of the first register and the first OR element, the inputs of the first groups of the second register and the register block, the outputs of the first, second and third groups of which are connected to the inputs of the first, second and the third multiplexer group, the outputs of which are the outputs of the first group of the device, the first output of the control unit is connected to the first inputs of the first reversible counter, the first and second registers, the outputs of the second register are connected to the inputs of the second OR element and the output of the first group of which is connected to the inputs of the second group of the second register, the outputs of the second group of the encoder are connected to the inputs of the fourth group of the multiplexer and the outputs of the second group OR is an output device request. FIG. 1 shows a block diagram of the proposed device for entering information; in fig. 2 and 3 - time diagrams. The device for entering information contains block 1 of comparators 1, a digital-to-analog converter (D / A converter) 2, first 3 and second A reversible counters, first element ELI 5, first register 6, second register 7, block 8 registers, element AND 9, second element OR 10 , encoder 11, multiplexer 12, control unit 13, first 14 and second 15 inputs of the device, first and second inputs 16 and 17 of the control block, respectively. The information input device operates as follows. The input analog signals are supplied to the inputs of the first group of block 1 of the comparators. The input of the DAC 2 signal is fed to the input of the compiler 1 unit. At the initial moment of time, the control unit 1 generates signals for the initial installation of reversible counters 3 and 4, the counter 3 most significant bits are set to 00 ... O, and the counter 4 the lower-order bits are 11 ... 1. At the same time, registers 6 and 7 are set to zero. CDL converts the codes of reversible counters to voltage. The comparators compare the voltages, input and from the DAC, to determine if any input signal is in the range corresponding to a voltage equivalent to the difference of the quanta of counters 3 and 4. If such signals are present, the comparators of these channels are set to one , at the output of the OR 5 element, a logic level 1 appears, which enters the input of the control unit 13, which forms a pulse clock sequence, which, arriving at the subtracting input of the reversing counter t, reduces its content, and thus ue to the DAC until it becomes a voltage lower than the input channel (channels). If such a signal is one, the comparator of this channel goes to the zero state, forming a negative differential at its output. By this difference, my counters 3 and 4 contain only the register of the channel in which the comparators were dropped. The same differential sets the triggers of this channel in registers 6 and 7 to one state. The trigger signal of register 6 arrives at the prohibitory input of the corresponding comparator and keeps it in the zero state until the beginning of the next conversion cycle. The appearance of a logical 1 in register 7 causes the appearance of 1 and the output of the element OR 10, will generate an external device request signal. If the signals in several channels coincide with the accuracy of the DAC, then several comparators are reset and the process proceeds in parallel for several channels. If at the end of writing to the registers the element IGSH 5 is still in state 1, then the process of subtraction - counter 4 continues until the conversion to the code of the last input signal in the dz-range. As a result, all activated comparators return to the initial state, the OR 5 element. 1. Simultaneously, according to the signal of the control unit 4, it is reset to the initial state (11 ... 1), which corresponds to the range of the second quantum of the counter 3. If the OR 5 element does not change its state (none of the comparators worked) 5 account content ika 3 sequentially incremented by 1, Once the element 1 enters SHI 5 edin1gchnoe state, the control unit switches tak.tovto sequence to the counter 4, etc. As soon as the last input signal is converted, all the triggers of register 6 appear in STATE 1 and the element 9 5 transmits to block 13 the control

lazy the end of the conversion cycle.

The information input process is performed independently of the conversion process of the appearance of the request signal at the input of the element OR 10. The input is performed synchronously with the external control signals on the first input 14 of the device. Upon the arrival of a positive differential of this signal, the encoder 11 generates at its outputs the positional and binary codes of the highest number of the specified priority trigger from all the trigger registers 7 set to one. The binary code at the output of the encoder 11 controls the multiplexer 12, and the binary outputs go to the device outputs channel codes and signal values in this

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channel. The position code of the given channel after the end of the reading of the codes resets the corresponding trigger register 7 to the initial state, 5 If by this time conversion occurs in other channels and any other triggers of register 7 are set to 1, then the OR 10 element supports a single input on its output. level, t, e request signal. On the next read cycle, the read process is repeated until the request signal is removed,

15 Thus, the average analog input cycle time is reduced. The degree of reduction depends. from the particular distribution of input levels over a range and

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Claims (1)

INFORMATION INPUT DEVICE, comprising a comparator unit, a digital-to-analog converter, first and second reversible counters, a first OR element, a first register, an AND element, an encoder, a control unit, the first input of which is the second input of the device, the second output of the control unit is connected to the second input of the first a reverse counter, the third and fourth outputs of the control unit are connected to the first and second inputs of the second reversible counter, respectively, the third input of the control unit is connected to the output of the first element nt OR, the digital-to-analog converter output is connected to the input of the comparator unit, the inputs of the second group of which and the inputs of the AND element are connected to the outputs of the first register, the output of the And element is connected to the second input of the control unit, the encoder input is the first input of the device, the inputs of the first group of the comparators block are inputs device groups, characterized by TDM, which, in order to improve performance by organizing independent processes for converting information and its operation according to request signals, it contains a second register tr, the second OR element, a multiplexer and a block of registers, the inputs of the second and third groups of which and the inputs of the first and second groups of the digital-to-analog converter are connected to the outputs of the first and second reversible counters, respectively, the outputs of the comparator unit are connected to the inputs of the first register and the first OR element, the inputs of the first groups of the second register and block of registers, the outputs of the first, second and third groups of which are connected to the inputs of the first, second and third groups of the multiplexer, the outputs of which are the outputs of the first group devices, the first output of the control unit is connected to the first inputs of the first reversible counter, the first and second registers, the outputs of the second register are connected to the inputs of the second OR element and the encoder, the outputs of the first group of which are connected to the inputs of the second group of the second register, the outputs of the second group of the encoder are connected to the inputs the fourth group of the multiplexer and are the outputs of the second group of the device, the output of the second element OR is the output of the Request device. L 115