SU1438008A1 - Code converter - Google Patents

Abstract

The invention relates to computing and can be used to convert a binary code to a Fibonacci code. The aim of the invention is to increase speed. The converter comprises a switch 1, an adder 2, a register 3, a memory block 4, a code comparison block 5, a control block 6. 1 hp f-crystals, 3 tab., 3 Il.

Description

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four:

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The invention relates to a computational technique and can be used to convert a binary code into a Fibonacci code.

The purpose of the invention is to increase the speed of the converter.

Fig, 1 shows the Jonapna function code converter circuit; Fig. 2 is a functional block diagram of the control unit J in Fig. 3; timing diagrams of the operation of the code converter.

The code converter comprises a switch I, an adder 2, a register 3, a block 4 of memory, a block 5 of comparison of codes and a block 6 of control,

The control unit 6 is formed by elements I.PI 7 and 8 ,, elements NOT 9 and 10, elements 11-13, registers 14 and 5, triggers 16 and 17 and counter 18 "

Converter codes works as follows.

The second input of the control unit 6 receives the clock frequency. After the TorOj, as the input bus of the converter, the converted binary code is fed, the Nachao conversion command is sent to the first input of the control unit 6. On this command, registers 14 and 15 and counter 18 are zeroed, trigger 16 is set to state 1, s, and trigger 17 is zero, switch 1 connects wake-up inputs of register 3 to the input bus and sends a signal to receive 1 Demo on control the input of the register 3 from the output of the element OR 83 information is recorded in the register 3, after which from the output of the register 3 information is fed to the second input of the block 5 of the code comparison

Counter 18 forms the address of the equivalent weight of the Fibonacci code, which must be fed to the first inputs of block 5, which compares codes from memory block 4,

At the initial moment of the conversion, the contents of counter 18 are equal to zero, which indicates the zero addressj at which the equivalent of the highest Fibonacci code weight is written. The address value from counter 18 to steps on the third inputs of memory block 4.

Trigger 17 divides the clock frequency in half. Upon the arrival of the first clock pulse, it is set to single. From the direct output of the trigger 17- to the first input of the memory block 4

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impulse arrives. Resolution with shtyvani. Upon the arrival of this pulse, a binary equivalent of the weight of the Fibonacci code appears at the second outputs of memory block 4

Using the code comparison block 5, a comparison is made of codes received from the outputs of register 3 and memory block 4 On the first output of code comparison block 5, the unit appears if the contents of register 3 are greater than the weight of the Fibonacci code, otherwise zero. At the second output of block 5, a code comparison appears in the case that the contents of register 3 are greater than zero. These signals arrive at the third and fourth inputs of control unit 6. Using the elements OR 7 and NOT 9, two bits of the output code are formed, which, on the leading edge of the pulse 3 formed by the AND 12 element, are written to registers 14 and 15, and are shifted by one bit and even bits are written to register 14 - yes, and in register 15 - odd.

After that, a second address for memory block 4 will be fully formed. This address consists of two parts. The first part (the two least significant bits of the address) consists of the last two bits of the output code that are removed from the outputs of registers 14 and 15, and the bits that are removed from the output of the reg20

25

thirty

35

0

five

0

five

gistra 14, determines the address bit with a weight of two9. and the bit, the first from the output of register 15, determines the address bit with a weight of one. The second. the part (the remaining address bits) is the address formed by the counter 18 "

Upon the arrival of the second clock-pulse, the trigger 17 changes its state and the resolution, read-w, is sent to the second input of the memory block 4, then the input of the adder 2 receives the binary equivalent of the Fibonacci code weight to be subtracted. However, positive the weights are written in the additional code, and the negative ones are in the direct one, the operation of reading. replaces the addition operation;

According to the signal arriving at the control unit, the input of the register 3, the result of the addition through the switch 1 is written to the register 3 at the same time

holding the counter 18 is increased by one.

The first conversion cycle is completed.

All transformation cycles, except for the last one, differ from the one described in that they do not reset the registers and do not record information from the input bus (there is no conversion start command).

The last conversion clock is characterized in that upon the arrival of the nth clock pulse at the transfer output of counter 18, a transfer pulse appears, which sets the trigger 16 to the zero state, which, in turn, prohibits the passage of clock pulses through the AND 1I element. At this point, the output code is fully formed and recorded in registers 14 and 15, starting from the second bits, since a shift occurs after recording the information.

Thus, the conversion cycle is completed, the output code is in registers 14 and 15, the outputs of which form the output bus, and the outputs of register 14 are even, and the outputs of register 15 are odd bits of the output code.

Let the size of the output code. The input of the converter receives the number +12. In binary code, it is represented as

Zn 16 8 4 2 1

About 01100

Upon the arrival of the command to start the conversion, switch 1 connects the input bus to the inputs of register 3 and impulses from the OR 8 element the input information is written to register 3 and is fed to the first input of the adder 2 and the second input of block 5 of the comparison to the virgins. At the same time, registers 14 and 15 and counter 18 are zeroed, and the trigger; 16 is set to unit state.

The third inputs of memory block 4 are followed by the zero address at which the binary equivalent of the tenth one is written.

TO 9 34 -21 1 1

87654321 12 -8 5 -3 2 -1 10 O 1 10 11 11,

which corresponds to the maximum form of the number +12 in the Fibonacci code, and

0

0

five

Fibonacci weights. When switching to the unit state of the trigger 17, the Read Enable command is received at the first input of the memory block 4, after which the first inputs of the code comparison block 5 receive information from the memory block 4. Thus, block 5 analyzes two codes: from the output of register 3 - O 01100 and from the second outputs of block 4 of memory - O 100010. In this case, the value is convertible: less than the weight of the Fibonacci code and more than zero .. Therefore, the third and fourth 5 the inputs of block 6 are received respectively 1 and 1. As a result, the elements OR 7 and NOT 9 form two bits of the output code 1 1, which are recorded on registers 14 and 15 on the leading edge of the pulse from element K 12, respectively, and information in these registers is shifted.

The address for memory block 4, arriving at its fourth inputs, is now fully formed. The address will be 000011. The first four older bi-, that is the address formed by the counter 18, and the last two bits - the last bits of the output, which are removed from the second bits of the outputs of registers 14 and 15. Upon the arrival of the second clock pulse, the code is added, recorded in register 3, and the code received from the second inputs of adder 2 from memory block 4.

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five

five

0

0

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1100

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one

one

Register 3 Block 4 memory (first outputs)

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On the leading edge of the pulse from the output of the element OR 8, the result of the addition operation is written to register 3.

The first conversion cycle is completed. The following conversion cycles are performed similarly. In the dash, an example of converting the number +12 is presented in the form of table 1.

At the end of the fifth cycle of operation of the converter in registers 14 and 15, the output code will be generated:

even bits are written in register 14, and odd bits are in register 15.

For a more complete understanding of the operation of the converter, Tables 2 and 3 are given - permanent firmware tables

memory devices of memory block 4

Claims (1)

1. A code converter containing a register, the outputs of which are connected to the first inputs of the adder, and an elastic control unit, the first output of which is connected to the control input of the register, which is different there 4TOj in order to increase the speed of the comparison unit codes and switch j whose first information inputs are the information inputs of the converter, the outputs are connected to the information inputs of the register, the first input of the control unit is combined with the control input of the switch and it is the installation the input of the converter, the second input of the control unit is the clock input of the converter J, the second j, the third, fourth and fifth outputs of the control unit are connected to the corresponding inputs of the memory unit, the first inputs of which are connected to the second inputs of the summerJ the outputs of which are connected to the second information inputs of the switch; the second outputs of the memory unit are connected to the first inputs of the code comparison unit, the second inputs of which are connected to the register outputs, the first; and the second outputs of the code comparison unit are connected respectively to the third and fourth inputs of the etching unit, the sixth outputs of which are information outputs of the converter. 2, the Converter according to claim 1, of which the control unit contains triggers, registers, counter, elements OR, elements AND the HEj elements of the output of the first element OR and the output of the first element are NOT connected to the information inputs of the first and second registers; the direct output of the first trigger is connected to the first input of the first element AND, the output of which is connected to the input of the second element NOT and the single input of the second trigger, direct and inverse outputs of which are connected respectively to the first inputs of the second and third elements AND., the output of the second element is NOT connected to the second inputs of the second and third elements AND, the output of the second element AND is connected to the clock the first and second registers j output the third element I. is connected to the clock input of the counter and the first input of the second element OR, the transfer output of the counter is connected to the zero input of the first trigger, the installation input of the counter is combined with the installation inputs of the first and second registers, single and zero inputs the first and second triggers and the second input of the second element OR is the first input of the control unit, the second input of the first element AND is the second input of the control unit, the first input of the first element G is combined with the input of the first element NOT and is the third input of the control unit J the second input of the first element OR is the fourth input of the anchor unit, the output of the second element OR the forward and inverse outputs of the second trigger are respectively the first - third inputs of the control unit. the information outputs of the counter are the fourth outputs of the memory unit, the information outputs of the counter and the low-order outputs of the first and second registers are the fifth outputs of the control unit, the outputs of the first and second bits Registers are the sixth outputs of the control unit. Table 2. Adding a memory block of the adder (third inputs - second outputs) Table 1 Table3  Firmware A memory block (fourth inputs - first outputs) I Code I O Yu0010 O 001101 O 000101 O 000010 O 000001 Fibonacci code weight 34 13 5 2 one nptofpauldHUHnpfofpaieffaffuf ii 15ns; it 4ffw; Cj 4: WHC; t. 4 SOONS; if too not Rag. 3