SU1345350A1 - Device for varying binary code sequence - Google Patents

Abstract

The invention relates to automation and computing and can be used in devices for converting binary codes that change the order of bits. The aim of the invention is to increase speed. The device allows you to change the order of the number of consecutive numbers. The device is adaptive to changing the code length. The device contains a shift register 1, an element OR 8, a counter 10, a trigger 9, six AND elements which are connected by information links ensuring the operability of the device. 1 il. (L with s 4 JV CO JV

Description

 134

The invention relates to automation and computing and can be used in devices for converting binary codes that change the order of bits.

The purpose of the invention is to increase speed.

The drawing shows a functional diagram of the device.

In the figure, the following symbols are used; shift register 1, elements AND 2-7, element OR 8, trigger 9, counter 10, information 11 and current 12 inputs of the device, output 13 of the device.

Counter 10 is built according to the counter scheme with a variable conversion factor determined by the resolution of the converted binary number. The number of bits of the code K to be converted must satisfy the inequality KM, where M is the size of the shift register.

The device works in the following way.

Let the input 11 be sequentially, the least significant bits ahead come the binary number code. The trigger 9 is in the zero state. Counter 10 with a variable conversion factor is set to mod K. When K is fed with input pulses at input 12, the number code in low-order bits is written to the shift register 1 with the help of shift signals to the right, coming through the open element II. To the overflow signal, the trigger 9 is set to one. When the second code arrives at the input 11, the last one is written to the left through the open element AND 6 into the shift register 1 with the help of shift signals left through the element AND 3. At the same time through the open element AND 7 and the element OR 8 with the help of shift signals to the left, the first number is output by the device 13 output by the senior bits ahead. Thus, at output 13, we obtain the sequential output of the transformed code of the first number by the leading bits ahead with a delay of K cycles.

VNIIPI Order 4932/55 Circulation 899

Random polygons pr-tie, Uzhgorod, st. Project, 4

0

15

20

In register 1, the second number is found in K cycles, the overflow signal from the output of counter 10 changes

This trigger 9 is zero, and when the next clock pulses arrive, the second number code is transmitted by the high bits forward through AND 5, OR 8 elements at output 13, and the third number is written in low bits forward through the AND element 4 into register 1 using the shift signals to the right, coming through the element 2.

Similarly, the sequential turn of the binary numbers, which arrive in the high bits, is reversed.

Claims (1)

Invention Formula A device for changing the order of the binary code containing a counter, an OR element, first, second and third AND elements and a trigger, the zero and one outputs of which are connected to the first inputs of the first and second AND elements, respectively, characterized in that, in order to improve speed , the fourth, fifth and sixth And elements and the shift register, the outputs of the first and last bits of which are connected to the first inputs of the sixth and fourth And elements, respectively, are entered into it, the counter input is connected to the clock input m devices and second inputs of first and second AND gates, and its output - with counting input of the flip-flop, the zero output of which is connected to the first input of the third and the second input of the fourth AND element, the output latch unit connected to the first input of the fifth and second the input of the sixth And elements, the information input of the device is connected to the second inputs of the third and fifth And elements, the outputs of which are connected respectively to the first and last bits of the shift register, the left and right shift inputs of which are connected to the outputs of the first and second elements And, the fourth outputs and the sixth AND elements are connected via the OR element to the output devices. Subscription