SU1285605A1 - Code converter - Google Patents

Abstract

This invention relates to automation and computing. Its use in digital computers and discrete automata allows to increase the conversion speed. The code converter contains a counter, triggers, shift register, pulse shaper, pulse generator, AND elements, delay element, and key blocks. The introduction of the OR element and the NOT element, as well as the organization of the reverse operation of the counter and the shift register, made circular, provides a reduction in the time it takes for the counter to reset. The code converter has a simpler execution than the decoder solving the same problem for six or more bit input codes. 1 il. (L

Description

the half of which is equal to 2, where n in, pi

one

The invention relates to automation and computing technology and can be used in digital computers and machines of discrete action.

The purpose of the invention is to increase speed.

The drawing shows the functional diagram of the code Converter.

The code converter contains counter 1, the OR element 2, the generator of 3 pulses, the first trigger 4, the first 5 and the second 6 elements AND, the N-shift shift register 7, the first 8 and second 9 blocks, the keys, the third 10 and the fourth 11 the elements And, the second 12 and the third 13 triggers, the element IE 14, the element 15 delay, the driver 16 1 pulses. In addition, inputs 17, first 18 and second 19 outputs are marked.

 The shift register 7 is made ringed, and in the initial state in its zero position one is written, in the others - zero.

Code Converter works as follows.

From the inputs 17, the information (binary code) is fed into the cells of the counter 1. When information appears in the cells of the reversible counter, the single outputs of the counter appear one-to-one | 1e signals. These signals through the element OR 2 are sent to the generator 3 pulses, which leads to the inclusion of the latter. Single pulses from the output of the generator 3 are fed to the first inputs of the first 5 and second 6 elements I. If the counter 1 records the number, capacitance,

the number of counter cells, i.e. if the counter contains a number greater than 2 (and this is possible when the full cell of counter 1 is filled), then the output of the last cell of counter 1 is named after it. single signal. This single signal triggers the first trigger 4. A single signal from the direct output of the trigger 4 is fed to the second input of the first element 5, and the pulses from the output of the generator 3 are fed to the summing input of the meter. At THIS, meter I is filled (the meter is running for summation). The final filling of counter 1 occurs when

all its cells are recorded by a single signal. The next pulse coming from generator 3 leads to overflow of counter 1, i.e. in all its cells, zero signals appear, while generator 3 is turned off.

five

0

five

0

five

0

five

0

The pulses from the output of the first element And 5 are also fed to the input of the second trigger 12 and to the input of the direct shift of the ring register 7 of the shift. We will conditionally assume that when pulses are received from element 5, the shift in the ring register 7- occurs to the right, and when pulses are received from element 6 - to the left. After the arrival of pulses at the input of the ring register 7 shift, i.e. when the generator 3 is turned off, a single signal is set in one of the cells of register 7. The zero signal from the output of the element OR 2, the passage through the element NOT 14, arrives as a single signal at the first input of the third element AND 10. At the second input of the element 10 it receives a single the signal from the direct output of the trigger 12. Therefore, at the output of the element And 10 there is also a single signal, which is fed to the control input of the first block of 8 keys. This allows a single sig -: alu from the ring shift register 7 to arrive at one of the first outputs 18. After the zero signal appears at the output of the OR 2 element, a single signal from the output of the NOT element 14 is fed to the delay element 15 and the driver 16. Delay element 15 sets the duration of a single signal. at the output of the code converter.

If a number less than 2 is written in the reversible counter 1, then in the last cell of counter 1 there is no single signal, i.e. The first trigger 4 does not work. While a single signal from the output of the trigger 4 is fed to the input of the second logic element And 6 and the counter 1 is working on the subtraction. With this mode of operation of the counter 1, there comes a time when all the cells of the counter 1 will have zero signals. As a result, the generator 3 is turned off. When the counter is working on subtracting a single signal in the ring register 7, the offset is left from the left, and after the generator 3 is turned off at the output of the second unit

9 keys the output of the code converter appears.

Thus, due to the reverse operation of counter 1 and register 7, the conversion of a binary code to a single positional one (from, n) occurs in time proportional to

bulk / t 4 I

The proposed converter is preferable to use when the input code is not lower than 6, then its execution requires less in terms of elements AND the number

-

logical elements, data decoders.

what dl known

Claims (1)

Invention Formula A code converter containing a counter, an N-bit shift register, where N 2, n is the input code width, triggers, pulse generator, pulse shaper, AND elements, delay element, and key blocks, characterized in that speed increase, the OR element and the NOT element are entered into it, the shift register is made ringed, the OR element output is connected to the element input NOT and the control input of the pulse generator; the output of which is connected to the first inputs of the first and second elements AND, the outputs of the counter are connected to the corresponding inputs of the OR element, the output of the most significant bit of the counter is connected to the input of the installation in the unit of the first trigger, direct and inverse you five  ABOUT 15 25 0 30 35 the strokes of which are connected to the second inputs of the first and second elements AND, the output of the first element AND are connected to the summing input of the counter, the installation input to the unit of the second trigger and the direct shift input of the shift register, the output of the second element AND to the subtracting input of the counter, the installation input into the unit of the third trigger and the input of the reverse shift of the shift register, the output of the element is NOT connected to the first inputs of the third and fourth elements AND, and through the delay element to the input of the pulse former, the output cat It is connected to the inputs of the installation of the shift register and the inputs for setting the flip-flops to zero, the inverse outputs of the second and third flip-flops are connected to the second inputs of the third and fourth And elements, the outputs of which are connected to the control inputs of the first and second key blocks, respectively; from the first to (Ы-2) -th are connected to the corresponding information inputs of the key blocks, the output of the (N-1) -th bit of the shift register is connected to the corresponding information input of the first block of the key whose counter inputs are the corresponding converter inputs, the outputs of the first key block are the corresponding first outputs of the converter, the output of the N-ro shift register and the outputs of the second key block are the corresponding second outputs of the converter. 17 ./ r i i i