SU1037309A1 - Displacement to parallel converter - Google Patents

Abstract

1. A MOVEMENT TRANSMITTER INTO THE PARALLEL CODE containing a code element, sensitive elements arranged by the V method, the outputs of sensitive elements are connected to code conversion inputs, characterized in that, p. In order to increase the reliability of the output code of the converter, a register and a inhibit impulse generator, whose output is connected to the control input of the register, are entered into it; the second control input of which is connected to the source of the survey. O: l With “9 O with

Description

2. The converter according to claim 1, similarly in that the inhibitor signal driver contains the elements NOT, AND, NONE, OR NONE and the delay element whose output is connected to the first input of the first element NAND and NOT through the first element - with the first input of the second NAND element, the output of the second NAND element is connected to the first input of the OR OR NO element, the output of which is connected to the first input of the AND element, the output of the AND element is connected to you

the course of the former forbidding them. pulse, the first control input of which is connected to the second input of the second NAND element and the inputs of the delay elements and the second element NO, the output of the second element is NOT connected to the second input of the first AND element, whose output is connected to the second input of the OR-NOT element, the second input element And is connected to the second control input of the inhibit pulse generator.

The invention relates to automation and computing and can be used to communicate analog information sources with digital computing devices.

A known displacement transducer to a parallel code comprising a code element associated with a displacement object, fixedly reinforced sensing elements, and a code converter lj.

The underperformance of this converter is not high enough that the readability of the code corresponds to the angular position of the shaft because of the relatively long conversion time of the binary-shifted code to the lithmetic one.

 Closest to the invention to the technical essence is a displacement transducer to a parallel code comprising an n-bit code element, a sensitive element for the first discharge and two sensitive elements for each subsequent discharge of the code element. The outputs of the sensitive elements of all bits are connected to the inputs of the code converter zj.

A disadvantage of the known converter is the insufficiently high accuracy of the output code, since a situation of reading a false code is possible during transients of converting a binary to arithmotic code.

The aim of the invention is to increase the reliability of the output code.

The goal is achieved by the fact that in the displacement transducer into a parallel code containing a code element, sensitive elements arranged by the V-method, the outputs of sensitive elements are connected to code conversion inputs, a register and a prohibitor driver are inputted, the output of which is connected to the control input of the register, the outputs of the code converter are connected to the information inputs of the register, while the first output of the code converter is connected to the first control input of the generator of the inhibit and pulse, the second control input of which is connected to the source of the survey.

The fop 1ho prohibitor signal contains the elements NOT, AND, NAND, ILIN and a delay element whose output is connected to the first input of the first NAND element and through the first element NOT to the first input of the second NAND element, the output of the second AND element Is NOT connected to the first input of the element OR NOT, whose output is connected to the first input of the element AND, the output of the element AND is connected to the output of the inhibitor pulse former, the first control input of which is connected to the second input of the second element NAND and the inputs of the delay elements and second element E, output of the second NOT member soedimen s.vtorym input of the first AND-NO element whose output is connected to a second input e ment NOR second input of AND gate is connected to the second control input of prohibiting impylsa. FIG. Figure 1 shows a flowchart for converting movement to parallel code; in fig. 2 - diagrams of transients that occur at the output of the code converter when changing the code 0111 to 1000; in fig. 3 diagrams of the operation of the elements of the inhibitor impulse. The converter contains code element 1, sensing elements 2 arranged by V-read method, code converter 3, shaper pulse generator k, including delay element 5, elements NOT 6 and 7, element AND-NE 8 and 9, element OR-NOT 10 and the element And And, register 12 and the source 13 of the survey. The Converter operates as follows. With an arbitrary position of the code element, the sensitive elements 2 read the information, which is digitized and fed to the inputs of the converter 3 of the code. To write the output code of the converter to an external device, the driver + transient pulse and the register 13 are used. In FIG. Figure 2 shows, for example, the process of changing the four-bit code 0111 to code 1000. The plots in Figure 2 (a, b, c, and d) correspond to the JO code changes of the first, second, third, and fourth bits at the outputs of the converter 3 code. When the V-method is read, the converter 3 of the code works in such a way that each subsequent bit starts the conversion after the previous one ends. Therefore, when the code is changed, there will be a delay in the conversion of a code with a duration of tpp. For example, the time for converting code 0111 to code 1000 will correspond if it is conventionally assumed that t is the delay caused by the transition time of the sensing element from the state of a logical zero to a state of logical one or from a logical one to a logical zero. The generator t of the inhibit signal from the moment of any change in the state of the first-digit code generates a write inhibit impulse to the register 12, the duration of which must be longer than the conversion time. The inhibit pulse is generated both when the code of the first code of the first bit changes from O to 1, and from 1 in O. In the first case, the write inhibit pulse is formed by the AND-HE element 8 (FIG. 3 d) from the signal of the first bit directly (Fig. 3a) and the signal of the first bit code delayed by delay element 5 (fig. 3c) and NOT 6 inverted by element 6. In the second case, the write inhibit pulse is formed by AND-HI element 9 from delayed by delay element 5 | code of the first bit and inverted by the inverter 7 of the signal of the code n The first bit (fig.Z b). The write inhibit pulses (fig.Z e and e) are summed by the element OR-NOT 10 (fig.Z g) and arrive at the first input of the element IV, prohibiting the arrival of pulses from the outputs of the converter 3 of the code in the register 12. The duration of the inhibit pulses will be determined . jj delay element, so it should be chosen a little more conversion time. As a result, writing to the register can occur only after the conversion of the binary-shifted code into arithmetic is completed, and the recording of false code values appearing in transients after changing the code at the outputs of the sensitive elements will be excluded. The conversion error will not exceed the unit of the least significant bit. The economic effect of using the proposed converter is determined by its technical advantages,.

and,

2

Claims (2)

1. A TRANSFER FOR MOVING IN A PARALLEL CODE containing a code element ', the sensitive elec- trodes of the sensitive elements are connected to the code conversion inputs, characterized in that, in order to increase the reliability of the converter output code, a register and a shunt pulse generator are inserted into it, the output of which is connected to the control input of the register, the outputs of the code converter are connected to the information inputs of the register, while the first output of the code converter is connected to the first control input of the barring pulse generator, the second control input of which is connected to the source 2. The Converter according to claim 1, characterized in that the driver of the inhibit signal contains the elements NOT, AND, AND, NOT, OR NOT and a delay element, the output of which is connected to the first input of the first element AND NOT through the first element NOT - with the first input of the second AND-NOT element, the output of the second AND-NOT element is connected to the first input of the OR-NOT element, the output of which is connected to the first input of the AND element, the output of the AND element is connected to the output of the driver of the inhibiting pulse , the first control input of which is connected to the second input of the second element AND E and the inputs of the delay elements and the second element NOT, the output of the second element is NOT connected to the second input of the first AND-NOT element, the output of which is connected to the second input of the OR-NOT element, the second input of the AND element is connected to the second control input of the inhibit pulse generator.