SU1594705A1 - "1 of n" code checking device - Google Patents

Abstract

The invention relates to computing and can be used in digital equipment control equipment. By providing an analysis of several bits of a controlled stroke during a single period of the clock frequency, it increases the speed of the device. The device contains the element OR 1, the counters 2 and 3 pulses, the multiplexer 4, the decoder 5 zero and the adder 6. 1 Il.

Description

(L

WITH

Yu

SP

;about

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The invention relates to computing technology and can be used in equipment controlling digital equipment.

The purpose of the invention is to understand the speed of the device.

The drawing shows a functional diagram of the device

The device contains an element

OR 1, the first and second counters 2 and 3 pulses, multiplexer 4, decryption-1 | ator 5-zero., And adder 6. Figures 7-9 denote information inputs, control input and device installation input. Accordingly, position 10 - output device.

The device works as follows.

Before the start of operation, the signal from input 9 counters 2 and 3 are set to the zero state. The information inputs of multiplexer 4, input 7, receive an n-bit controlled cDV. Multiplexer 4 begins interrogating the code by three bits. On the rising edge of the clock signal from input 8 on the counting input, the state of counter 2 and the code combination on the address inputs of multiplexer 4 change. On a low level of the clock signal, the polled three bits of the code are transmitted to the inputs of the Totalizer 6,

N-bit code does not contain a single 1, then at the output of the decoder

A 5n signal forms a logical 1, which is fed through the element OR 1 to the input 10 of the device as an error signal. If the code to check contains one 1,

then at output 10, the error signal does not match. If the code being checked contains more than one 1, then two options for device operation are possible. The first option: if two or more I are contained in three simultaneously polled code bits, in this case the output of the transfer is

6po is a logical 1, which is through an element. OR 1 goes to the output of device Yu as a signal: an error. The second option: if one by one

G is contained in several successively polled triples of bits, in this case, the output signal is the sum: adder 6 is fed to the counting input of counter 3, and the error signal at output 10 is generated by logical 1 at the output of the second discharge of counter 3,

In the case when,, and t, d, t, e, when n is not a multiple of three to the inputs of multiplexer 4, which add to the multiplicity of three, zero signals are constantly given.

Thus, the device implements the analysis of several controlled-code bits (three bits) simultaneously in a single clock frequency period.

Claims (1)

Invention Formula A device for monitoring code 1 of p, containing pulse counters, a multiplexer and a decoder zero whose output is connected to the first input of the OR element whose output is the output of the device, the bit outputs of the first pulse counter connected to the corresponding address inputs of the multiplexer, the second pulse counter output connected to the second input of the OR element, the counting input of the first pulse counter is combined with the multiplexer control input and is the control input of the device, the inputs of the decoder zero volume Dineny with the corresponding information inputs of the multiplexer and are the information inputs of the device, the installation inputs of the first and second pulse counters are combined and are with the installation input of the device, which is mainly due to the fact that, in order to decrease the speed of the device, an adder is entered the sum of which is connected to the counting input of the second pulse counter, the multiplexer outputs are connected to the corresponding inputs of the adder, the transfer output of which is connected to the third input of the OR element,