SU1383321A1 - Smooth periodic function generator - Google Patents

Abstract

The invention relates to automation and computing and can be used as a precision generator of smooth periodic functions. The purpose of the invention is to simplify the generator. The generator contains a clock generator 1, counter 2, elements 3, 7, 9, element 8, memory block 4, shift registers 5, 6, reversible counter 10, block 11 of setting initial conditions. The introduction of a reversible counter and two shift registers into the generator makes it possible to reduce the capacity of the memory block and thereby simplify the design of the generator. 2 Il.

Description

S a

(t)

OS OS 00

oo

N3

The invention relates to automation and computing and can be used as a precision generator of smooth periodic functions.

The purpose of the invention is to simplify the generator.

FIG. 1 shows a functional diagram of the generator; in fig. 2 - timing diagram of the generator.

The generator contains a clock generator 1, counter 2, element 3, memory block 4, registers 5 and 6 of shift, element 7, element 8, element 8, element 9, a reversible counter 10, block AND setting initial conditions, a digital-analog converter 12.

The generator of smooth periodic functions works as follows.

The clock generator 1 generates high-frequency pulses (diagram 13, fig. 2), arriving at the counting input of counter 2 and the input of element AND 3. The direct inputs of the element AND 3 receive the code of lower bits of counter 2, and the inverse inputs - code older bits The diagrams (Fig. 2) illustrate the operation of the function generator, containing a four-bit counter 2, changing its state on the trailing edge of an even pulse, and memory block 4 (GTZU) with a capacity of four eight-bit words, and the four most significant bits of each word are the increment codes of the function in the four quantization sections, and the four least significant bits are the signs of these increments. After the appearance in the counter 2 of a code containing zeros in the leading bits and one in the lower ones (for the given example, the OOP code), the output of the element I 3 appears a pulse coinciding in time with the next generator pulse 1 (chart 14, fig. 2). The impulse from the output of the element I 3 is fed to the input of the recording resolution of the reversible counter 10. On the leading edge of this impulse, the initial value of the reproduced function is recorded in the counter 10 (Fig. 17, Fig. 2). In addition, when a code in the counter 2, containing all the units in the lower bits (UN, 0111, 1011, 1111), appears at the output of the And 7 element, a unit potential appears (Figure 15, Fig. 2) arriving at the inputs controlling the operation mode of registers 5 and 6. As a result of this, the latter go into the mode of writing the code received from ROM 4 to their information inputs. On the leading edge of the next (in this example, the fourth, eighth, twelfth, and sixteenth) pulse of generator 1, a multi-digit code is recorded in register 5, which determines the absolute values of the increments on several (in this example, four) next quantization sections. At the same time in the register 6 written code of the characters of these increments. Increment sign code

0

0 5 g

0

five

0

five

0

Yes, the high-order bit of register 6 (diagram 16, fig. 2) is fed to the input of the control of counter 10 and, depending on the sign, switches it to the summation mode or to the subtraction mode. Simultaneously, from the output of the high bit of register 5, the value of the function increment in the next quantization section arrives at the input of the And 9 element. The second input of the element And 9 receives pulses from the output of the element HE 8, generated by the zero value of the signal at the output of the generator 1. With a single increment value at the output of the element And 9, a pulse is formed (Figure 18, Fig. 2), which coincides in time with a single a signal at the output of HE 8. This pulse arrives at the counting input of counter 10 and, depending on the signal at the control input, increases or decreases its code by one. At the output of the D / A converter 12, the value of the reproduced function is formed on the next quantization stage (diagram 19 of Fig. 2).

With a zero signal at the control input, the registers 5 and b go into shift mode, which is performed on the leading edge of the output pulses of generator 1. After the shift to higher bits of registers 5 and 6, the function increment code and the sign code of this increment are received in the following quantization section. In addition, on the trailing edge of the generator 1 pulses, the counter 2 code increases. After each 2 pulses of the lower bits of counter 2 (in the example), go to the zero state, and the high bits of the counter 2 simultaneously change. The inputs of ROM 4 receive the new value of the address, however, the read word in registers 5 and 6 is completed after an interval of 2 times the 2 output pulse generator I periods.

Claims (1)

Invention Formula A generator of smooth periodic functions comprising a clock generator, a counter, a memory unit, the clock generator output being connected to a clock input of the counter, the output of which bits is connected to the address input of the memory block, which, in order to simplify the generator, it contains two shift registers, a reversible counter, a block for setting initial conditions, three AND elements, an element NOT, and the output of the lower bits of the counter is bitwise connected to the corresponding direct inputs of the first and second elements And, the output of the high bits of the counter is bitwise connected to the corresponding inverse inputs of the first element, And the first and second outputs of the memory unit are connected to the parallel inputs. the first and second shift registers, respectively, the control inputs of which are connected to the output of the second element And, the serial output of the first shift register connected to the first input of the third element And, the output of which is connected to the counting input of the reversible counter, the serial output of the second shift register connected to the control the counter direction input of the reversible counter, parallel information input of the reversing 13 J lJgglJgglLJJplJllLLLgggl 15, rm P 17 rLTLJl /five lrmjinjirLTUTnji- l u The control input is connected to the output of the first element, the output of the reversible counter is the generator output, the output of the clock generator is connected to the clock inputs of the first and second shift registers, to the corresponding inputs of the first and the second element L and through the element NOT to the second input of the third element I. rm rm rm l ffU8.2