SU1539770A1 - Associative function converter - Google Patents

Abstract

The invention relates to computing and can be used in the construction of functional transducers of monotonically varying linear digital codes, such as functional transducers of angular displacement into a digital code. The purpose of the invention is to reduce the amount of equipment by reducing the amount of memory in which there is no function value field. An associative functional converter containing a counter 5, a comparison circuit 2 and an equivalence domain memory block 1, whose inputs are connected to the counter outputs, a single pulse generator 4 and an OR 3 element are entered, the outputs of the equivalence domain memory block 1 are connected to the first circuit inputs 2 comparisons, the output of which is connected to the input of the generator 4 of a single pulse, the output of which is connected to the first input of the counter 5, the inputs of the associative functional converter are connected to the second inputs of the comparison circuit 2 and the inputs of the OR 3. In memory block 1, codes are written corresponding to the input codes denoting the equivalence regions of the output codes. If the input signals are equal to the code of the signals read from memory block 1, the contents of counter 5 change by one. From the output of counter 5, the code of the desired function is read. 1 il.

Description

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a lax equivalence whose inputs are connected to the counter outputs, a 4 single pulse generator and an OR 3 element are entered, the outputs of the equivalence domain memory block 1 are connected to the first inputs of the comparison circuit 2, the output of which is connected to the single pulse generator 4 input, the output of which is connected with the first input of the counter 5, the inputs of the associative functional converter are connected to the second inputs of the comparison circuit 2 and the inputs of the element OR 3. In the memory block 1, the codes corresponding to the input codes are labeled aspirants boundaries of the equivalence of output codes. If the input signals are equal to the code of the signals read from memory block 1, the contents of counter 5 change by one. From the output of counter 5, the code of the desired function is read. 1 il.

The invention relates to computing and can be used in specialized converters that process monotonically varying linear digital codes.

The purpose of the invention is to reduce equipment costs.

The drawing shows the functional diagram of the Converter.

The converter contains a block of 1 memory of equivalence domains, a comparison circuit 2, an element OR 3, a generator 4 of single pulses, a counter 5, an input 6 of the argument, an input 7 of the initial value of the function, an output 8 of the sign of the beginning of transformations and an output 9 of the function.

The Converter operates as follows.

In block 1 of the memory of equivalence domains, the values corresponding to the boundary values of equivalence domains (i.e., areas in which, when the input

signals the function code remains constant). The code stored in counter 5 contains the address of the next domain of equivalence. The code read from block 1 of the equivalence domain memory is compared in comparison circuit 2 with a monotonically varying code at input 6 of the argument.

When the codes are equal, the generator of 4 single pulses produces a signal according to which counter 5 is changed by one, i.e. the value of the function at the corresponding output 9 of the converter is changed. Function value not

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varies until the input code reaches the next boundary value of the equivalence domain. The OR 3 element is used to initialize the counter 5 to the state corresponding to the value of the function at zero input code.

Claims (1)

Invention Formula An associative functional converter comprising a counter, a comparison circuit and a memory of equivalence domains, the counter outputs are connected to the address inputs of a memory of equivalence domains, characterized in that, in order to reduce equipment costs, a single pulse generator and an OR element are inserted into it, moreover, the outputs of the memory block of equivalence regions are connected to the input of the first operand of the comparison circuit, the input of the second operand of which is connected to the input of the argument of the converter and the corresponding The input inputs of the OR element, the output of the equality sign of the comparison circuit is connected to the trigger input of a single pulse generator, the output of which is connected to the counting input of the counter, the input gate of the initial record of which is connected to the output of the OR element, the output of which is connected to the output of the sign of the beginning of converters connected to the output of the counter, the information inputs of which are connected to the inputs of the initial value of the converter function.