SU1659997A1 - Comparison number device - Google Patents

Abstract

The invention relates to automation, computing and digital measurement technology and can be used in measurement systems and tolerance control. The purpose of the invention is to increase speed. The device contains a pulse generator 1, a counter 2, counting registers 3, 4, a decoder 5, triggers 6, 7, the AND element 8, and the OR elements 9-11 with corresponding connections. 1 il. 1 tab.

Description

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The invention relates to automation, computing and digital measurement technology and can be used in measurement systems and tolerance control.

The purpose of the invention is to increase speed.

Diagram of the device shown in the drawing.

The device contains 1 pulse generator, counter, counting registers 3.4, decoder 5, triggers 6. 7, element AND 8, elements OR 9-11, start input 12, initial setting input 13, outputs More than 14, Less than 15 and In tolerance 16 .

Before the device starts operation, the controlled value X is entered into counter 2, the counters 3 and 4, respectively, the lower H and upper B tolerances, and, by a signal at input 13, the triggers 6 and 7 are set to zero. Then to the input 12 receives a potential signal 1 which starts the generator 1

pulses and enters the gate input of the decoder 5, which operates in accordance with the table.

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The decoder 5, by the value of the high-order bits, I, X, B, determines in which half of the range, senior or junior, these values lie, and, depending on

from this sets the modes of addition or subtraction of counters 2, 3, 4.

Let X B, Then the following situations are possible.

1.XN, B N, where N is half the capacity of the counters 2, 3, 4. Then, at the inputs H, X, the decoder 5 has signals 0,1,0, which corresponds, according to the table, to the signal at the output A1 which goes to output 14 of the device and means that.

2.N N, B N. Then, at the inputs H, X, B of the decoder 5, signals 0,1,1 are set, which corresponds to the signal at output A4, With this signal, counters 2 and 4 are set to subtraction mode, and "after a while when the value of B becomes less than N, the signals 0, 1.0, discussed above, will be set at the inputs of the decoder 5.

3 .. Then the signals 1, 1, 1 will be set at the inputs of the decoder 5, which corresponds to the signal at its output A3. Counters 2, 3, 4 will be set to subtraction mode, and after some time, when H, decreasing, becomes less than N, the signals O, 1, 1, discussed above, will be set at the inputs of the decoder 5.

4.X N. At the inputs of the decoder 5 will be set signals O, O, O, which corresponds to the signal at its output A6. The counters 2, 3, 4 will be set to the summation mode, and when X increases to N, the signals 0, 1, 0, discussed above, will be set at the inputs of the decoder 5.

The operation of the device in cases when X H is similar to the cases considered up to the sign of the operating modes of the counters 2, 3, 4. In this case, a signal is generated at the output 15 of the device.

Let H X B, and X N. The following options are possible.

5.N Н X В. Then the signals 1,1,1 are installed at the inputs of the decoder 5, which corresponds to the signal at the output A3. Trigger 6 is set to one, and counters 2, 3, 4 are in subtraction mode. When H becomes less than N, signals 0.1, 1 will be set at the inputs of the decoder 5, and then, when X becomes less than N, signals 0, 0, 1, which corresponds to the signal at the A5 output of the decoder 5. This signal will set the trigger 7 in a single state, and at the output of the element And 8 and the output Tb of the device, a single signal is indicated, meaning that B.

6.N V. The device works in the same way, however, the values of H and X reach N simultaneously, therefore after the state 1,1,1 inputs of the decoder 5 the state 0,0,1 immediately appears.

7. N N. The device operates as described in claim 5, however, after the state 0,1,1 of the decoder inputs, a state 0,0,0 occurs (since the values X and B reach

N values at the same time). In this case, a signal appears at the output of the A6 decoder, which also sets the trigger 7 into a single state, and so on.

Operation of the device in cases where

0 Н Х В, moreover, X N, is similar to the considered cases with an accuracy of the sign of the operating modes of the counters 2, 3, 4 and the order of installation of the triggers 6 and 7 in the unit state.

5 After forming a signal at one of the outputs 14, 15, 16 of the device, the signal that stops the pulse generator 1 is generated at the output of the element OR 9.

Claims (1)

0 claims A device for comparing numbers, containing a counter, registers of upper and lower tolerances, two triggers, a decoder, a pulse generator, the And element and the first and 5 second elements OR, and the device start input is connected to the start input of the pulse generator, the output of which is connected to the counting input of the counter, the output of the AND element is connected to the first input of the first 0 of the OR element, the input of the initial installation of the device is connected to the inputs of the installation of both triggers in the zero state, which is due to the fact that, in order to increase the speed, a third 5, the OR element, and the upper and lower tolerance registers are countable, and the counting inputs of the counter of odd registers of the upper and lower tolerances are combined, and the outputs of their higher bits are connected, respectively, with the first, second and third information inputs of the decoder, the first and second outputs of which are The outputs More and Less are respectively, and are connected respectively to the second and third inputs of the first OR element, the output of which is connected to the stop input of the pulse generator, the start input of which By connecting the input of the decoder strobi- ruyuschemu third output 0 which is connected to the installation input of the counting register of the lower tolerance into the subtraction mode and with the first input of the second OR element, whose output is connected to the inputs of the installation into the subtraction mode of the amp and the counting register of the upper tolerance, the fourth output of the decoder the upper tolerance register in addition mode and with the first. the input of the third OR element, the output of which is connected to the inputs of the installation in the addition mode of the counter and the counting register of the lower tolerance, the fifth and sixth outputs of the decoder are connected to the second inputs of the second and third OR elements, respectively, the outputs of which are connected to the inputs of the installation in one state respectively the first and second triggers, the direct outputs of which are connected respectively to the first and second inputs of the element I, the output of which is the output B of the device tolerance. C