SU1277359A1 - Programmable pulse generator - Google Patents

Abstract

The invention can be used in frequency sensor signal simulators, automation, software control systems. The aim of the invention is to increase reliability. To achieve the goal, the delay element 3, the equivalence element 5, the AND elements 8, 9, the OR 10 element, the inverter 4, the triggers 2, 11 are entered into the pulse generator. The programmable generator also contains a pulse counter 1, a step delay line 6, a multiplexer 7. This programmable generator reduces the volume and complexity of the equipment. 1 il.

Description

(Y)

WITH

The invention relates to a pulse technique and can be used in simulators of signals of frequency sensors, automation, software control systems.

The aim of the invention is to increase reliability by reducing the amount of equipment used.

The drawing shows a functional diagram of the programmable pulse generator.

The generator contains a pulse count 1, a counting trigger 2, a delay element 3 with two outputs, an inverter 4, an equivalence element 5 for two inputs, a step delay line 6, a multiplexer 7, AND elements 8 and 9, an OR element 10, an RS flip-flop 11, The input buses 12 and 13 set the code for the pulse duration of the pulse pulse, the output 1A of the device, the input 15 reset the counter 1 to zero. The asynchronous input 16 of the counting trigger serves to start the device.

The subtracting input of the pulse counter 1 is connected to the counting input of the counting trigger 2, to the output of the element OR 10, and to the installation input to the RS flip-flop unit 11. The transfer output of the pulse counter 1 is connected to its pre-recorded input and to the Reset input of the RS flip-flop 11. The output of the counting trigger 2 is connected with the input of the delay element 3, the first output of which through the inverter 4 is connected with the first input of the equivalence element 5, and the second output - with the second INPUT of the equivalence element 5, the output of which is connected to the first input of the And 8 element and sequentially connected delayed delay line 6 and multiplexer 7 with the first input of the element I 9, the second input of which is connected to the direct output RS-flip-flop 1 and the inverse output of which is connected to the second input of the element 8. The outputs of the elements 8 and 9 are connected with The current inputs of the element OR 10, The input bus 12 is connected with the information of the counter 1 pulses. Input pshia 13 is connected to the control input of the multiplexer 7, Input i 5 is connected to the reset input of the pulse counter 1.

. The device works in the following way.

Before running on the bus 12, the counter 1 and the bus I3 multiplexer 7

codes are set which correspond to the required duration of the output pulse period. Further, by applying a pulse to the input 15, the counter 1 is zeroed. By changing the start pulse through the asynchronous input 16 of the counting trigger 2, its state changes. In this case, the differential from its output enters the input of the delay element 3, which passes directly and through the tap and the inverter 4, enters as two displaced and inverse relative to each other drops to the corresponding inputs of the equivalence element 5, at the output of which a pulse is formed, : whose ness corresponds to the shift of the drops that came to the input. The retraction of the delay element 3 to the inverter 4 is chosen in such a way that the pulse produced by the output of the element 5 has a duration sufficient for sure gating of all elements realizing the device. The impulse from the output of the equivalence element 5, passed through, the element I8 and the element OR 10, is fed to the counter subtraction input and the counting input of the trigger 2. At the transfer output of counter I, a pulse arises that goes to the output of the device simultaneously at the pre-recording input the counter i writes a code into it from the input bus 12, and on the input S it sets the RS trigger for one state. At the same time, the counting flip-flop 2 changes its state, with the result that the output of element 5 is the next pulse, which, in accordance with the code specified on the input bus 13, passes from the corresponding output of the stepped delay line 6 through multiplexer 7 to the first the input element 9, on the second input of which from the direct entrance of the RS flip-flop is set to one. Passing through elements AND 9 and ITS 10, the pulse changes the state of trigger 11, the state of counting trigger 2 and the state of counter 1. In this case, RS trigger 11 allows the passage through element 8, counter 1 contains the code; reduced by one and the output

trigger 2, a drop occurs, along which at the output of element 5 a regular impulse is formed, which, having passed through the elements AND 8 and OR 10,

Claims (1)

Invention Formula A programmable pulse generator containing a pulse counter, a step delay line, the outputs of which are connected to the multiplexer inputs, characterized in that, in order to increase reliability of operation, a delay element, an equivalence element, two AND elements, an OR element, an inverter, a counting and RS triggers, where the information inputs of the pulse counter are the first input bus of the device, the output of the counting trigger is connected to the input of the delay element, the outputs of which, one directly and the other through an inverter, are connected to the corresponding inputs of the equivalence element, the output of which is connected to the input of the stepped delay line and the first input of the first element And, the output of the multiplexer is connected to the first input of the second element And, the outputs of the first, second elements And connected to the corresponding inputs of the OR element, the output of which is connected to the counting input of the counting. the trigger, the subtraction input of the pulse counter and the installation input into the RS flip-flop unit, the direct and inverse outputs of which are connected respectively to the second inputs of the second and first elements AND, the transfer output of the pulse counter is connected to the reset input of the RS flip-flop, with preliminary recording BXOAON counter vtg The device input bus is connected to the control input of the multiplexer. Proofreader M.Sharoshi