SU1187169A1 - Device for checking synchronizing buses - Google Patents

Abstract

A SYNCHRONIZATION BUS CONTROL DEVICE containing four triggers, a Reset button, the first and second elements are NOT, and the outputs of the triggers are information outputs of the device, characterized in that it contains the third element NOT, the four And elements and the And element -NO, the trigger synchronization is connected to the first controlled synchronization bus, with the first input of the first element AND and the input of the first element NOT, the synchronous input of the second trigger is connected to the second controlled synchronization bus , with the first input of the third element AND and the input of the second element NOT, the synchronous input of the third trigger is connected to the third controlled sync bus, to the input of the third element NOT and the first input of the second element AND, the output of the first element is NOT connected to the first input of the fourth element AND and the second input of the second element, the output of the second element is NOT connected to the synchronization input of the fourth trigger and the first input of the fourth element AND, the output of the third element is NOT connected to the second inputs of the first and third elements AND, 3 output The first, second, third, and fourth elements d are connected to the information inputs of the fourth, second, first, and third flip-flops, respectively; the single inputs of the first, second, third, and fourth flip-flops are combined and connected to the first contact of the Reset button, the second contact of which is connected to the bus the unit potential of the device, the outputs of the first, second, third, and fourth triggers of the geres are connected to the first, second, third, and fourth inputs of the AND – NOT mud, respectively, the output of which is you the course of the device error.

Description

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The invention relates to computing and can be used to control synchronization buses of measurement and control systems, for which the timing relationship between clock signals is important.

The purpose of the invention is to increase speed.

FIG. 1 shows a block diagram of the device; in fig. 2 is a timing chart of monitored synchronization signals.

The device contains triggers 1-4, elements NOT 5-7, elements AND 8-11, element AND NOT 12, the first bus 13 synchronization, the second bus 14 synchronization, the third bus 15 synchronization, output 16 errors of the device, information outputs 17 of the device, Reset button 18.; The device works as follows.

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At the initial moment of time when the button 18 is pressed, a positive impulse will set all the triggers 1-4 to the state of a logical unit. The state of the triggers does not change when the bus 14 goes to a low level — a logical zero; the transition is possible only after a high level appears on the bus 13 — a logical unit The high state on the bus 15 is possible only after the bus 14 has been installed, and then bus 13 in a low state. The transition of the bus 15 to the low level state is possible only if there is a high level on the bus 14 (Fig. 2a).

The transition of the bus 14 to the low level state in the absence of a high level state on the bus 13 switches the trigger to the logical zero state and the error signal is output at the output of the device 16 (Fig. 26), and the exit code 17 will be fixed with a failure code.

Claims (1)

DEVICE FOR CONTROL OF SYNCHRONIZATION TIRES, containing four triggers, a Reset button, the first and second elements of NOT, moreover, the outputs of the triggers are information outputs of the device, characterized in that, in order to improve performance, it contains the third element of NOT, four elements of AND and the element And NOT, moreover, the trigger sync input is connected to the first controlled synchronization bus, with the first input of the first AND element and the input of the first element NOT, the second trigger sync input is connected to the second controlled synchronization bus, from the first m the input of the third element AND and the input of the second element NOT, the sync input of the third trigger is connected to the third controlled synchronization bus, with the input of the third element NOT and the first input of the second element AND, the output of the first element is NOT connected to the first input of the fourth element And and the second input of the second element And , the output of the second element is NOT connected to the synchronization input of the fourth trigger and the first input of the fourth element And, the output of the third element is NOT connected to the second inputs of the first and third elements And, the outputs of the first, second th, third and fourth elements AND are connected to the information inputs of the fourth, second, first and third triggers, respectively, the unit inputs of the first, second, third and fourth triggers are combined and connected to the first contact of the Reset button, the second contact of which is connected to the unit potential bus of the device, the outputs of the first, second, third and fourth triggers are connected to the first, second, third and fourth inputs of the AND-NOT element, respectively, the output of which is the error output of the device.