SU1378033A1 - Device for checking clocking frequency pulses - Google Patents

Abstract

The invention relates to a pulse technique and can be used in clock synchronization systems, as well as in systems with a redundant generator for monitoring clock pulses. The aim of the invention is to improve the reliability of the control. To achieve this goal, the first trigger 6 is designed as a D-trigger and an additional pulse distributor is introduced, the second 3 and third 4 pulse counters and D-triggers 7 and 8. In addition, the device contains a pulse distributor 1, counter 2, logical element 5, bus 9 and 10. Monitoring at the end of each signal period of the clock frequency of the synchronized generator is provided by introducing counters, whose operation cycles are shifted by the clock interval. Timing diagrams illustrating the operation of the device are provided in the specification. 2 Il. cl

Description

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The device relates to a pulse technique and can be used in clock synchronization systems, as well as in systems with a redundant generator for monitoring clock pulses.

Figure 1 shows the structural electrical circuit of the device; on

during the first period, information is output from the output of the second discharge of the counter to the corresponding synchronous D-trigger and setting the initial state of the counter on the counter reset input, and for the two remaining periods there is a controlled simulator. 2 — time diagrams , on which Q clock pulses, incoming signals are denoted by signals a ... m, marked at the nodes of the circuit of FIG.

A device for monitoring clock pulses contains a pulse distributor 1, the first — the third 5 counters, respectively, 2–4, the AND 5, the first — the third synchronous D-flip-flop, respectively, 6–8. The clock signal from the synchronized generator is fed 20 to the first bus 9, the output signal is removed from the bus 10. The input (monitored) clock signal is fed to the second input bus 11.

The input of the distributor 1 of pulses 25 is connected to the first input bus 9, the first output is connected to the reset input of the first counter 2 and the C input of the first D flip-flop 6, the second output to the reset input of the second counter 30 3 and the C input of the second D- trigger 7, the third output of the distributor 1 is connected to the reset input of the third counter 3 and the C input of the third D-flip-flop 8, the outputs of which are connected to S5 inputs of the And 5 element, and the D inputs of the first, second and third D-flip-flops 6-8 are connected to the outputs of the second bit, respectively, of the first - the third counter 2-4, the counting inputs 40 of which are combined and connected to the second input bus P, the output of the AND 5 element is the output of the device.

The device for controlling pulses of the clock frequency works in the following 45 ways.,.

The clock frequency signal from the synchronized generator enters the bus 9. At the outputs of the distributor 1, non-overlapping pulses with a duration equal to the period of the clock frequency (timing diagrams c, d, d, Fig.2) are generated. Thus, at each output of the pulse distributor 1, the limits of the time interval of one cycle of operation of the corresponding counter are formed. The cycle of operation of one counter is equal to three periods of the clock frequency, and in

Shch1gkh on the counting input of the counter.

When two pulses arrive at the counting input of the counter during the time interval allocated for counting the controlled pulses of the clock frequency, a signal 1 is generated at the output of the second bit of this counter, indicating the required presence of controlled clock pulses.

In the absence of at least one of these two pulses, an output signal O is generated at the output of the second counter of the counter, indicating that the clock pulses have disappeared.

The iGuided information is read into the corresponding synchronous D-flip-flop and stored there until the beginning of the next cycle of the corresponding counter.

The implementation of control at the end of each period of the clock signal of the synchronized oscillator is achieved by introducing three counters, whose operation cycles are shifted relative to each other by the clock interval. Thus, at the end of each cycle, at the output of the corresponding synchronous D-flip-flop, information about controlled clock frequency pulses is generated (according to the presence or absence of the required number of clock frequency pulses).

The output signals of the first 6, second 7 and third 8 synchronous D-triggers are connected by an AND 5 logic element, the output of which is with the output of a clock pulse frequency monitor (time diagram m, Fig. 2).

Claims (1)

Invention Formula A device for monitoring so-called frequency pulses, containing the first and second buses of the clock frequency, the first pulse counter, the first trigger, the AND element, is characterized in that, in order to increase reliability, the first trigger is designed as during the first period, the information from the output of the second discharge of the counter is coupled to the corresponding synchronous D-flip-flop and the initial state of the counter is set at the counter reset input, and during the two remaining periods the counters are controlled by it. When two pulses arrive at the counting input of the counter during the time interval allocated for counting the monitored clock pulses, a signal 1 is generated at the output of the second bit of this counter, indicating that the clock pulses are monitored. In the absence of at least one of these two pulses, an output signal O is generated at the output of the second counter of the counter, indicating that the clock pulses have disappeared. The iGuided information is read into the corresponding synchronous D-flip-flop and stored there until the beginning of the next cycle of the corresponding counter. The implementation of the control at the end of each period of the clock signal of the synchronized generator is achieved by introducing three counters, whose operation cycles are shifted one relative to the other by the clock interval. Thus, at the end of each cycle, at the output of the corresponding synchronous D-flip-flop, information about controlled clock frequency pulses is generated (according to the presence or absence of the required number of clock frequency pulses). The outputs of the first 6, second 7, and third 8 synchronous D-triggers are connected by an AND 5 logic element, the output of which is the output of a clock pulse control device (time diagram m, figure 2). Invention Formula A device for monitoring clock pulses, containing the first and second buses of the clock frequency, the first pulse counter, the first trigger, the AND element, characterized in that, in order to increase reliability, the first trigger is designed as D-flip-flops, as well as a pulse distributor, second and third pulse counters, second and third D-triggers, the pulse distributor input connected to the first input bus, the first output - to the reset input of the first pulse counter and the C-input of the first D- trigger, the second output - with the reset input of the second pulse counter and the C-input of the second D-flip-flop, the third output - with the reset input of the third counter and the C-input of the third D-flip-flop, the outputs of which are connected to the inputs of the element I, and the D-inputs of the first, second and third D-flip-flops are connected to the outputs of the second discharge of the first, second and third impulses, respectively, counting inputs which are combined and connected to the second input bus, the output element AND is the output device. 1 oh 5 о S 6 g O , e o fK about 0 W. JTJl.fl | lJT..p | 5iriJ rtriJTutiJlijIuiuTJ Mil i ffnl L m FIG. g t MO