SU598226A1 - Arrangement for synchronization of pilot and reference digital signals - Google Patents

Description

(54) DEVICE FOR SYNCHRONIZATION OF CONTROL AND REFERENCE DIGITAL SIGNALS

go and reference digital signals; Fig. 2 shows the time diagrams of its operation (a is the operation of the device in the absence of synchronization, b-the moment of entering synchronization).

The synchronization device of the control and reference digital signals contains a block of clock frequency 1, a generator of reference signals

2, mismatch block 3, element NO 4 RS. - the trigger 5, the elements And 6, 7, the element is NOT 8, the decoder 9, the pulse counter 10 and the control signal bus 1 1.

The device works as follows.

The control signal bus 11 simultaneously enters the block 1 and block

3. Block 1 starts the generator 2 and the cutter 10. At block 3, a one-by-one comparison is made of the control and reference word with a length of 2 bits (bits). The signal of the presence of the first mismatch in the selected word sets the trigger 5 to the unit potential at the output (FIG. 2, outg. 5). In this case, when the signal from the output

and the decoder 9 on the element 6, a signal is generated to shift the reference sequence per clock.

The discrepancy signal is allowed to set a 5-unit potential at the output of the trigger in the first cycles of the counter 10, which corresponds to the length of the word to be extracted during the next 2 cycles of the counter 1.0 - is prohibited. Trigger 5 is read by the signal from the output of the decoder 9 and the zero potential is set at the output of the trigger 5 from the output to the decoder 9 after the discrepancy between the flip-flop 5 is disabled, and the zero potential is set at the output of the trigger 5 after the reading trigger status 5.

The cycle repeats until the time when no discrepancies are recorded, in this case, when the signal at the output of the decoder 9 is present, the sync end signal is generated on the element 7. Well, at the output of the element, a signal is formed.

continue synchronization The shift of the reference sequence per clock {figure 2, out. 6), and at the output of element 7 a signal is generated End of synchronization (FIG. 2, output 7), turning off the device. Introduction of an additional (n + 1) th digit of counts. This 10 allows you to eliminate the effect of the internal delay in the circuit consisting of 2-3-4-5-6 (8-7) -2 nodes and to divide in time the fixation of mismatches, their reading and return of the trigger 5 to the initial state.

Claims (1)

1. Levin, LS, Plotkin, MA Basics of building digital transmission systems. M., Svy, 1975, p. 117.