SU1226661A1 - Counter operating in "2-out-of-n" code - Google Patents

Abstract

The invention relates to automation and computing and can be used to build various devices for transmitting and processing information and testing devices of digital equipment. The aim of the invention is to enhance the functionality of the device by forming an equilibrium code, ordered in decreasing order of binary codes. The technical essence of the invention lies in the fact that a pulse distribution node and a trigger installation node are inserted into a counter containing a clock pulse generator and triggers. Another area of application is the use in devices for encoding and decoding equilibrium codes 2 of § 2 Il. g (L

Description

The invention relates to automation and computer technology and can be used to build various information transmission and processing devices and test equipment of digital equipment.

The purpose of the invention is to expand the functionality of the counter by generating code, ordered in decreasing order of a binary value.

FIG. 1 shows a functional diagram of the counter; in fig. 2 is a circuit implementation of a trigger.

The counter contains the pulse distribution node 1, the trigger setup node 2 and the triggers 3 (3.1 3.2, 3.3, ..., 3. (p-2), 3. (p-1), Z. p) ,. Node 1 contains the elements AND 4 (4.1, 4.2, ..., 4. (p-3), 4. (p-2). Node 2 contains the elements AND-HE 5 (5,1,.,., 5). (p-4), 5. (p-3), 5. (p-2)). The input 6 of the counter is connected to the first input of the element And 4. (p-2). The output of the element And 4. is connected to the clock input of the trigger - pa 3.J, where jl, ... n-2. input element And 4. connected to the output

element And 4. (5 + 1), where 1, p-3

The clock inputs of the triggers 3. (p-1) and Z. p are connected to the input 6. The second input of the element I 4.J is connected to the main inverse output of the trigger G 3. (j- + l). The main direct output of trigger 3.k is connected to the output 7.k of the counter (, ..., p-1) and to the first information input of trigger C 3. (k. + L). The main direct output of trigger Z. p is connected to the output 7.p. The second information input of trigger 3.4 is connected to the optional:, 1m inverse output of trigger 3. (k + l).

The main inverse output of the trigger Z.p is connected to the pulse inputs of the AND-NOT element. 5. The potential input of the AND-NE element 5 .. is connected to the additional direct output of the trigger 3. (. I + l). The output of the element .AND-NOT 5.J is connected to the installation input to the trigger one state 3. (j + 2

. Trigger 3.1, where, ..., p, contains (FIG. 2) RS-flip-flops 8 and 9 and I-NE 10 elements are 13. Flip-flop 8 forms signals at the main direct and inverse outputs of the flip-flop trigger, flip-flop 9 forms signals on additional forward and inverse trigger codes 3.1.

266612

Fundamental execution of the trigger 3.1 may be different. As well as node 1, whose purpose is to issue in a certain cycle

5 of the signal counter at a particular output, it does not necessarily have to be a chain of series-connected elements I.

10 The meter works as follows.

Triggers 3.1 and 3.2 are in the initial single state, and 3.3-3.p are in the zero state.

15 At the same time, at the direct outputs of the flip-flops 3. 1 and 3.2 are single potentials, and at the direct outputs of the flip-flops 3.3-H.p - zero. Node 1 provides signals only to the inputs.

20 triggers 3.2-3. P, where 2 is the number of the extreme right trigger, which is in the unit state, and the trigger 3.f is a zero potential from the main inverse output

25 blocks the signal to the clock inputs of the trigger 3.1-3. (D-1).

When the first pulse arrives from the input 6, the RS-flip-flop 8 of the flip-flop 3.3 switches to the single state, which then returns to the zero state the RS flip-flop 8 of the 3.2 flip-flop. At the end of the pulse, the RS-flip-flop 9 of the flip-flop 3.3 is switched to one state, and the RS-flip-flop | Ger 9 of the flip-flop 3.2 is set to the zero state. Further t each step of the counter in one state. The trigger switches 3.4, ..., 3.p are sequentially switched. At the same time, on the outputs, the codes P0 „.. 0, 1010 ... O, 10010 ... O, ..., 100...01. When in the unit state of the triggers 3.1 and Z.p, when the next pulse arrives in the unit state, it switches

 5 RS-flip-flop 8 flip-flop 3.2, and in zero - RS-flip-flops 8 flip-flops 3.I and Z. p. At the end of the pulse, the RS flip-flops 9 flip-flops 3.1 and ZP are switched to the zero state.

50 When switching to the zero state of the RS trigger 9 trigger Z.p, the signal from the main inverse output arrives at the inputs of the AND – NE elements 5. There is a single potential at the secondary

55 rum input of the element AND-NOT 5.1, at the same time at its output along the front-first front of the positive voltage drop at the inverse output RS30

35

40

the trigger 9 of the trigger Z.p. a negative polarity pulse is formed, which establishes the trigger in one state. 3.3. In this case, the code 0110 ... 0 is set at the outputs. Next as the pulses arrive, the counter operates in the described order, and at its outputs 7, the code 01010 ... O, then 010010, ... O, appears. ., 010, ... 01. Upon receipt of the next pulse, the triggers 3.2 and Z. p are zeroed, and the trigger 3.3 goes into one state. At the end of the pulse, a positive voltage drop from the inverse output of the RS flip-flop 9 flip-flop Z.p through the node 2 sets the flip-flop to a single state 3.4. Further, the operation continues in the same order until the counter transitions to the state in which the code O ... OI1 is written to it. The cycle of the counter is over.

In the next two clocks, the counter will completely zero. If necessary, the counter can be stopped in the state when the code 0 ... 011 is written to it.

Claims (1)

Invention Formula The counter in code 2 of p, containing n triggers, and a pulse distribution node, containing AND elements, differing in that. m L ... 7) one P rf 7J D5 t o1 J Lr R 81-1 26661 that, in order to expand the functionality due to the formation of a code ordered in decreasing order of a binary value, the counter 5 contains a trigger installation node containing AND-NOT elements, with the clock inputs of the first through triggers connected to the outputs of the corresponding elements AND of the pulse distribution node, the first input of each of which, (n-2) -th, is connected to the output of the subsequent, element AND of the pulse distribution node. first input (p-2) -th element 15 And the pulse distribution unit is connected to the counter input and the clock inputs (n-l) -ro and the n-th trigger, the second input of the j-ro element AND the pulse distribution unit is connected to 20 main inverse output (j + l) -ro of the trigger (, ..., p-2), the main direct output of the k-ro trigger is connected to the first information input (k + l) -ro of the trigger (kel, ... , p-1), 25, the second information input of the k-ro trigger is connected to the additional inverse output (k + l) -ro of the trigger, the main inverse output of the nth trigger is connected to the pulse inputs of the AND-NOT elements of the trigger installation node I -NOT the trigger installation node is connected to the additional direct output (j + l) -ro of the trigger, and the output is connected to the installation input in unit30 35 triggered state (j + 2) -ro. Hn-Z) one p-2) 3. {pp L one Itt-n7lIn. but one ...P fcbiM EoF (r.2