SU762206A1 - Circular frequency divider with odd division factor - Google Patents

Description

The invention relates to computing and can be used in devices for processing digital information.

Known annular frequency divider with an odd division factor, containing in each digit trigger, the element AND-NOT and the block forming a symmetric signal £ 1}.

A disadvantage of the known technical solution is its complexity and low immunity.

The closest technical solution to the proposed ring is a frequency divider with an odd division coeffi- cient ₁₅ comprising in each discharge trigger [2].

A disadvantage of the known technical solutions is low pomehousgoychi- _m ness.

The purpose of the invention is to improve the noise immunity of the ring frequency divider with an odd division factor.

2

The goal is achieved by the fact that in an annular frequency divider with an odd division factor, containing in each discharge a trigger, the clock inputs of which are connected to the input bus, the information input of each trigger of the subsequent discharge, except the first one, is connected to the single output trigger of the previous discharge, and zero output the trigger of the last digit is connected to the setup input of the trigger of the first digit, an additional H – NOT element is added, the first and second inputs of which are connected to the zero outputs of the flip-flops, respectively enno first and last digits and the output element and is coupled to the mounting trigger input all digits except the first.

FIG. 1 shows the principal electrical circuit of an annular frequency divider with an odd division factor; in fig. 2 - time diagrams.

An odd division coefficient frequency divider contains

h 762

triggers 1-1 - 1 (type D), element 'AND-NOT 2, input bus 3 and output ι tires 4-1 - 4— p.

The ring frequency divider with an odd division factor works as follows.

Suppose, in the initial state at time F, _the frequency divider is in the zero state. On its input bus 3 and output tires 4-1 - 4-and low voltage levels (see Fig. 2). At the zero output of the trigger 1-1 and the zero output of the trigger 1- {d high voltage levels that arrive at the inputs of the element AND — NOT 2. At the output of the element AND-NOT 2 low voltage level, which arriving at the inputs of the installation to zero triggers 1 -2 - 1st ,, confirms Their zero states. The high voltage level from the zero output of the trigger 1-P is fed to the input of the unit to zero and the information input of the trigger 1-1.

At the information inputs of the triggers 1-2 -1-p low voltage levels, respectively, coming from the single outputs of the triggers 1-1 - 1-P.

On admission at time. A trigger 1-1 is activated on the input bus 3 of the input frequency pulse, and at its single output of the bus 4-1 a high voltage level is set, which is fed to the information input of the trigger 1-2. At the zero output the trigger-: Gera 1-1 sets a low voltage level, which, acting on the input of the element AND-NOT 2, sets a high voltage level at its output, i.e. the suppressive low voltage level is removed from the installation inputs to the zero trigger 1 -2 - 1st.

With arrival at the moment of time 1. _{g, the} trigger 1-2 turns on at the input bus 3 of the next pulse of the input frequency and a high voltage level from its single output goes to the information input of the trigger 1-P. When an input frequency pulse arrives at the input bus 3 n -v of the input frequency, the last trigger 1-P divider turns on and a high voltage level is set at its single output 4 — V) and a low voltage level is set at the zero output, which arriving at the input of the setting to zero of the trigger 11 switches it, in addition, a low voltage level from the zero output of the trigger 1-P, arriving at the input of the element AND — HE 2, maintains at its output you—

four

soky level of tension. At the single output of the trigger 1-1 sets a low voltage level, which is fed to the information input of the trigger

1-2.

C. The arrival at the time of the next (Y + 1) pulse on the input bus 3 triggers the trigger 1-2, and a low voltage level is set at its single output and output bus 4-2 of the divider, which, acting on the information input of the next trigger, prepares its off. Thus, with each next input pulse, triggers are switched off sequentially. The trigger 1-P is turned off; at the moment of time the pulse arriving at the input bus 3 of the frequency divider (2η -1). At the single output of the 1-n trigger of the frequency divider, a low voltage level is set, and at the zero output, a high voltage level, which, acting on the information input and the installation input to the zero of the trigger 1-1, enables it to turn on.

In addition, a high voltage level from the zero output of the 1-P trigger arrives at the input of the I – BE 2 element (at its other input a high voltage level from the trigger 1-1 output), setting its low level at the output. voltage, which by the inputs of the installation to zero of the triggers 1-2 - 1-n, confirms their zero state or sets the trigger 1-2 - 1-n to the zero state, if they were in a single state due to interference operation.

With the arrival of successive pulses on the input bus 3 of the frequency divider, the division cycle repeats.

Thus, the ring frequency divider synchronously generates at outputs 4-1 - 4-n pulses, the duration of which is equal to ^ _(x - (P-1) T (5 _X , where P is the number of triggers in the divider, the repetition period of input pulses. following output pulses "2n-1) .- T% h.

The pulses at the outputs 4–1–4 are phase-shifted relative to each other, with an increase in the index n by T ^ ¹ *.

- hp-1

If the initial state of the trigger

the frequency divider is not zero or in the process of operation of the device occurs spontaneous switching of 'triggers

divider under the influence of interference then with

762206

The first and last triggers 1-1, 1-p of the divider will always be set to the zero state by the arrival of input pulses, while at their zero outputs there will be high voltage levels, which, entering the inputs of the AND-NOT 2 element, will cause a low level the voltage at its output and, therefore, the installation in the zero state, i.e. the initial state of the triggers 1-2 1-n divider. This setting occurs during all frequency division cycles, correcting the device in case of failures or confirming the state of the trigger of the divider. C

Building an annular frequency divider with an odd division factor according to the proposed scheme allows, without increasing the number of elements used in the circuit, to increase the reliability of the device by eliminating spontaneous changes in the division factor, i.e., eliminating simultaneous circulation in the divider for 25 times more than one the division cycle of several single signals, divided by pauses in the form of a zero signal.

Thus, the invention makes it possible to improve the noise immunity of the frequency divider with an odd ratio

division with minimal hardware costs.

Claims (1)

Claim An odd-dividing annular frequency divider containing a trigger in each digit, the clock inputs of which are connected to the input bus, the information input of each trigger of the subsequent discharge, except the first one, is connected to the single output trigger of the previous discharge, and the zero output of the trigger of the last discharge is connected to the setup input trigger of the first discharge, characterized in that, in order to improve noise immunity, an AND — NOT element is additionally introduced into it, the first and second inputs of which are connected to zero the outputs of the triggers, respectively, of the first and last digits, and the output elements. This AND-NOT is connected to the installation inputs of the triggers of all digits except the first.