SU1614095A2 - Infralow frequency signal generator - Google Patents

Abstract

This invention relates to a measurement technique. The purpose of the invention is to expand the frequency range of the output signals. Hr contains a source of reference voltage 1, D / A converter 2, polarity switch 3, low pass filter 4, constant memory block 5, rm 6 clock pulses, shift register 7, tunable rr 8 pulses, reversible counter 9 with a controllable number of bits, the elements of AND 10 and 11, the trigger 12 and the block 13 for setting the bit. The goal is achieved by including in the frequency range of signal generation not only the low-frequency, but also the low-frequency and sound regions. This possibility is provided by changing the bit size of the reversible counter 9 when switching from generating sinusoidal signals belonging to one frequency band to generating signals in another band. In this case, if the transition is made to a higher frequency region, then the width of the reversible counter 9 decreases, if in the direction of low frequencies, then the width increases. 1 il.

Description

The invention relates to a measuring technique and can be used in digital measuring equipment for various purposes.

The purpose of the invention is to expand the frequency range of the output signals.

The drawing shows a structurally evil, three-dimensional diagram of an infra-low frequency signal generator.

The infra-low frequency signal generator contains a reference voltage source 1, a digital-to-analog converter (DAC) 2, a polarity switch 3, a low-pass filter 4, a permanent memory block 5, a clock generator 6, a shift register 7, a tunable pulse generator 8, reversible counter 9 with a controllable number of bits, the first 10 and second 11 elements And, the trigger 12 and the block 13 for setting the bit.

The generator of infra-low frequency signals works as follows.

To generate a sinusoidal frequency signal Fi, the number N of the generation frequency range is predetermined according to a predetermined table and the frequency fnr of the clock sequence is calculated from the expression:

fnr 4 (2 - 1) FI,

where n N + 1 is the size of the reversible counter 9;

FI - set frequency of the generated signal.

The number N of the frequency range is given by the task block of size 13, and the frequency fnr is tunable to the generator 8.

The output signal from the tunable generator B pulses to the input of the reversible counter 9 with a controlled number of bits and causes a linear increase in the value of the code stored in it. When the reversing counter 9 overflows, it turns on for subtraction and the code value in it starts to decrease linearly. With a code equal to zero, the direct counting is turned on, the unit is entered into the most significant bit of the reversible counter 9, and the process is repeated. The unit from the high-order output of the reversible counter 9 is fed to the first inputs of the elements 10 and I. When the generator 6 of the next pulse is output, the second element 11 triggers, resulting in a pulse from its output to the installation input of the trigger 12 and translating it in a single state. Further pulses coming from generator 6 during the formation time

negative half-wave sinusoid, confirm the single state of the trigger 12. A single signal from the output of the trigger 12 is fed to the control input of the switch of the polarity body 3.

The pulses of the generator 6 clocks the writing of the code from the reversible counter 9 to the register 7. Thus, the inputs of the fixed memory unit 5 through the register 7 receive the codes from the reversible counter 9p by the frequency of the generator 6. The reversible counter codes 9 are address codes for block 5 of the permanent memory. With the arrival of the next address code, the next sample of the generated sinusoidal signal appears at the outputs of the 5 5 permanent memory module at its outputs. From the outputs of block 5 of the permanent memory, to-odes are fed to the information inputs of the DAC 2, the reference input of which receives signals from the source output, the output of the DAC 2 generates a signal of a unipolar step-like sinusoid approximation that goes to the input of the switch 3 field p-5 nosti. From the output of the latter, a two-pole stepped signal approximating the sine wave is transmitted to the low-pass filter 4, which smooths it.

0 After completion of the negative half-wave formation, when the reversible counter 9 passes with a controlled number of bits through a zero value, its highest bit enters 5 seconds to zero, which triggers the first element AND 10 through the next pulse from the generator output 6. Signal from the output of the first element, And 10 enters the other input of the trigger 12 and translates it to the zero state. As a result, the signal from the output of the trigger 12 switches the switch 3 to the mode of forming a positive half-wave signal.

The proposed solution provides 5 expansion of the frequency range of signal generation and the inclusion of not only the infra-low frequency, but also the low-frequency and sound areas. At the same time, there are no additional requirements 0 on the speed of the elements of the tunable pulse generator 8, the reversing counter 9 and the register 7. Achieving a positive effect is associated with a change in the size of the reversing counter 9 55 when switching from generating sinusoidal signals belonging to the same frequency range to generating signals in another range. In this case, if the transition is carried out in a higher frequency region, the counter size

reversible 9 decreases, if the transition is carried out in the direction of low frequencies - the size of the reverse counter 9 increases. In addition, when generating sinusoidal signals belonging to any of the specified ranges, the frequency of the pulse sequence at the output of the tunable generator of 8 pulses does not change more than twice.

Claims (1)

Claims of the invention The signal generator infra-low frequencies pa.st. № 1538216, so-called. that, in order to expand the frequency range of the output signals, the reversible counter is made in the form of a reversible counter with a controllable number of bits, the input of which the number of bits is connected to the output of the entered bit task block.