SU1429135A1 - Device for shaping sine signals - Google Patents

Abstract

The invention relates to computing and is intended to convert a series of variable square-wave pulses into a sinusoidal signal. The purpose of the invention is the expansion of functional capabilities due to the formation of a sinusoidal variable frequency signal with periods corresponding to periods. input signal. The device contains a clock generator 1, elements AND 2, 3, a counter 4, a decoder 5, a trigger 6, an approximation block 7, a fixed memory block 8, an AND 9 transmitter, a single-vibration 10, 11, a counter 12, a trigger 13, dual channel frequency divider T4. The number of generator pulses, corresponding to the half-period of the input square wave, determines the division factor of the frequency divider. Therefore, using a decoder, a stepped signal is formed with a variable period corresponding to the input one. The number of steps is constant and corresponds to the number of outputs of the decoder. 1 il. (L

Description

The invention relates to computer technology, and is intended to convert a sequence of rectangular pulses with a variable period into a sinusoidal signal.

The purpose of the invention is the expansion of functionality by forming a sinusoidal signal of variable frequency with periods corresponding to periods of the input signal.

The drawing shows a diagram of the device.

• 'The device contains a clock 1, first 2 and second 3 AND elements, first counter 4, decoder 5, first trigger 6, approximation unit 7, read-only memory unit 8, third AND element (coincidence) 9, first 10 and second 11 single-vibrators , second counter 12, second trigger 13 ,. two-channel divider 14 frequencies.

The device operates as follows.

The rectangular input pulses, by reducing the zero output, the decoder 5 switches trigger 6 to turn on the first element And again and switches the approximation unit 7 to negative polarity, after which a second half-period of sinusoidal oscillation is formed similarly.

When the duration of the input pulse changes, the code at the output of counter 12 changes; accordingly, the code of block 8 and the division coefficient of the frequency divider 14 changes, while the number of pulses at the output of the frequency divider remains constant; only the duration of individual pulses changes. As a result, when the duration of the input pulse changes, the duration of the steps changes, from 2Q of which a sinusoidal signal is formed.

Claims (1)

SUMMARY OF THE INVENTION A device for generating sinu25 signal-like signals containing a clock generator whose output is in the form of, a meander, is fed to the first input of an And 9 element, to the second input of which clock pulses from generator 1 are received, output pulses go to the input of counter 12, where half the signal period is determined. But before the count, he and trigger 13 are set to the zero position along the front of the input pulse and by a single-shot 10. Each value of the input signal half-cycle in block 8 corresponds to the setting code for the frequency divider 14. At the end of the pulse duration, the second one-shot 11 generates a pulse of information recording * and the start of trigger 13, which opens the first element And 9. By the way, the pulses outside come to the first (direct) input of the frequency divider 14 .. ⁴ After dividing the first η pulses (for example, η = 10) are sent to the counter 4, where they are converted into a code, according to which the growing part of the sinusoidal voltage is generated at the output of the decoder 5 and the approximation block 7. Upon reaching the maximum (n - 1) th (ninth) pulse, trigger 6 opens the And 3 element and the clock pulses arrive at the inverse input 55, as a result of which a decreasing voltage is generated at the output of the approximation block 7. It is connected with the first inputs of the first and second elements AND, the first counter, the output of which is connected to the input of the decoder, a group of η information outputs of which is connected to the information input of the approximation unit, the output of which is the output of the device, and the zero and nth outputs of the decoder are connected with the corresponding inputs of the first trigger, the direct and inverse outputs of which are connected to the second inputs of the second and first elements And, respectively, and the inverse output of the first trigger is connected to the control input of the polar approximation unit, characterized in that, in order to expand functionality by generating a sinusoidal signal of variable frequency with periods corresponding to periods *: input signal, the device contains a second counter, a third AND element, a second trigger, a read-only memory unit, a two-channel frequency divider and two single vibrators, the inputs of which are connected to the input of the device and the first input of the third element And, the output of the first single vibrator is connected to the inputs of zeroing the first and second counters and zero th input of the second flip-flop, whose output is connected with the third vho3 < dams of the first and second elements And, the output of the second one-shot is connected to the recording input of the frequency divider and to the unit input of the second trigger, the outputs of the first and second elements And are connected respectively to the inputs of the first and second channels of the frequency divider, the first and second outputs of which are connected respectively to the inputs addition and subtraction of the first counter, the clock output is connected to a second input of the third aND gate ₅ whose output is connected to the data input of the second account snip whose output is constant through the block constant memory coupled to the input for setting the frequency dividing ratio of Tell delied.