SU765983A2 - Infra-low frequency sinusoidal oscillation generator - Google Patents

Description

ha 9, the second shift register 10, the second additional reversible counter 11 and the additional output digital-to-analog converter 12,

The device works as follows) a3OM.

The pulse sequence from the output of the clock generator 1 is fed to the input of the reversible counter 2 and to the input of the logical element node AND-OR 4. The control unit 3 sets the operation mode of the reversing counter 2 in the following order: the first and third quarter of the generated signal - addition, second and fourth .- subtraction. Reversible counter 2 serves to control the node of logical elements IL-4, which provides pulses to the input of the reversible counter 5, and to the input of the reversible counter 11 via a controlled shift register 9 - only at times corresponding to the CTByHxivie in time to change the output signal by one quantization level.

The control unit b sets the following mode of operation for the reversible counter 5 and the reversible counter 11 connected to the control unit 6 via a controlled shift register 10 s: the first half-period of the added signal is addition, the second half-period is subtraction.

During the first quarter of the period of the generated signal, the successive codes of the reversible counter .2 and the node of the AND-OR 4 logic elements provide for the passage of pulses to the input of the reversible counter 5 and to the input of the reversing counter 11, at which digital-to-analog converters 7 and 12, which are used as code-voltage converters, produce the first quarter of the increasing portion of the sinusoid. Reversible counters 5 and 11 at this time operate in addition mode. When the first quarter period of the output signal is completed, the control unit 3 switches the reversible counter 2 to the subtraction, and the sequence of pulses at the input of the reversible counter 5 and the reversible counter 11 repeats in reverse order. The operation of the reversible counters 5 and 11 does not change in this interval , and the output signal continues to increase.

At the end of the formation of the first half-cycle of the sinusoidal signal, the control units 3 and 6 simultaneously switch the reversible counter 2 to the addition mode, and the reversible counter 5 and the reversible counter 11 through the controlled shift register 10 to the subtraction mode, and the described work cycle is removed from that the difference that the voltage at the outputs of the digital-to-analog converters 7 and 12 decreases according to the same law.

The phase shift of the signal at the output of the digital-to-analog converter 12 relative to the reference signal at the output of the digital-analog converter 7 is implemented by the controlled shift registers 9 and 10, which are shift registers with pre-recording the unit to one of its bits and restoring it after each cycle shift register operation.

A signal at the output of the controlled shift register appears with a delay relative to the input (initial pulse sequence) for a certain time, which in general can be defined as

tx t - t; denoting t nt;

pt,

ti

(-1) t (nrp),

get where J is the period of the next clock pulses;

n is the total number of bits of the shift register,

p is the number of the bit in which the unit is written. The discreteness of the initial phase is determined by the expression

, (2)

where k is the number of steps of the generated sinusoidal signal per period.

The signals from the node output of the logical elements AND-OR 4 arrive at the output of the reversible counter 11 with a delay defined by the expression (1). Thus, the output of the D / A converter 12 receives a sinusoidal signal shifted relative to the reference signal at the output of the digital-to-analog converter 7 on certain phase angle. The phase shift is proportional to the number of clock periods delayed by the controlled shift register and taking into account expressions (1) and (2).

 r (p-p) Af (| 1-p).

The setting of the required phase angle is made by entering a unit into one of the bits of the shift register. Managed shift registers 9 and 10 operate synchronously. The task of the latter is the switching of the operation modes of the reversible counter 11.

The technical and economic effect is to ensure a smooth adjustment of the initial phase of the oscillations, which expands the range of application of these data to the harmonic oscillations of the infra-low frequency in radio measurements and phase metering, for example, in estimating the errors of the phase calibrators.

Claims (1)

Invention Formula Sine-wave oscillator infra-low frequency auth.St. 40516 other than that In order to ensure smooth adjustment of the initial phase of oscillations, a second additional reversible counter and an additional digital-to-analog converter are connected in series; the first shift register is entered between the output of the AND-OR logic element node and the signal input of the second additional reversing counter, and between the output The control unit of the first additional reversible counter and the control input of the second additional reversible counter is entered in the second shift register. Sources of information taken into account in the examination 1. USSR author's certificate  405162, class H 03 B 19/12, 1972 (prototype).