SU819946A1 - Measuring converter - Google Patents

Description

(54) MEASURING CONVERTER

one

The invention relates to measurement technology and can be used in computing and measuring devices in control and automation systems as a precision multiplier-making device.

A dividing device with a DC output voltage is known, containing an input pulse frequency divider, a pulse selector, with which the pulse frequency rate is divided into a query by a clock frequency pulse serially connected to the DC filter 1.

The disadvantage of this dividing device is the presence of a low-frequency component at the output of the dc filter, which is caused by the unevenness of the pulse following the output of the pulse selector due to the non-synchronization of the frequency-pulse sequences at its inputs.

The closest in technical essence to the invention is a measuring transducer containing an input

a driver, a pulse selector, which contains a standby multivibrator or a clock pulse counter and a dc filter, including a source of pulses. and a smoothing

filter 2. In this converter, a decrease in the amplitude of the low-frequency component at the output is achieved by using a standby multivibrator or a clock counter in the pulse selector. However, in this case, the frequency of

clocking pulses should be significantly higher than the frequency of the periodic signal at the input of the input driver. Thus, the disadvantage of the considered converter is that it has a limited range.

operating frequencies and low speed, in the case of using it, for example, as a multiplying-dividing device.

The aim of the invention is to increase

speed and extension of the operating frequency range of the device.

This is achieved by the fact that the measuring transducer containing the input

the request pulse generator, the pulse selector and the dc filter, an additional pulse selector, the OR element, a trigger and two clocks memory blocks, the outputs of which through the OR element are connected to the input of the dc filter, and the clock inputs of the main and additional pulse selectors are combined and form a clock input of the measuring converter, and the outputs of the main and additional pulse selectors are connected to the first inputs of the first o and the second memory block of the clock pulses, while the direct output of the trigger is connected to the input of the main pulse selector and the second input of the second memory block of the clock pulses, and the inverse output of the trigger is connected to the input of the additional selector and the second input of the first memory block of the pulse, and the counting input of the trigger is connected to the output of the input driver pulse request.

FIG. 1 is a circuit diagram of a converter; in fig. 2 - timing diagrams of elements included in the converter.

The measuring transducer contains an input driver 1 request pulses, trigger 2 main pulse selector 3 and the first block 4 of the clock memory, an additional pulse selector 5 and the second block 6 of the clock pulse, the element OR 7 and the DC filter 8.

The measuring transducer operates as follows.

Let, in the established mode, from the input driver of the request 1 pulses, the rectangular pulses arrive at the counting input of the trigger 2, the period of which is equal to T (see Fig. 2, a). At the same time, on the direct (see Fig. 2, b) and inverse (see Fig. 2 c) outputs of trigger 2, there are pulses with a duration of Ti with a follow-up period of 2 T. At the input of the main 3 and additional 5 pulse selectors, clock pulses arrive the period of which is equal to Tj (see Fig. 2, d). Both the main 3 and the additional 5 pulse selectors form a pulse with a duration Tj at their outputs upon receipt of the enabling signals from trigger 2. The output signal of the first pulse selector 3 is shown in FIG. 2, and the output signal of the second pulse selector 5 in FIG. 2, d

Obviously, for the pulse selector to work properly, the condition T. | 2Tj

The first 4 and second 6 blocks of memory of clock pulses memorize the duration T g of pulses, which come from pulse selectors 3 and 5.

The first memory block of the clock pulses 4 reproduces a pulse of duration T g (see Fig. 2, h) when a request is received from the direct output of the trigger 2, and the second memory block of the clock pulses 6

reproduces a pulse of duration T2. (see Fig. 2, g) upon receipt of a request from the inverse output of trigger 2.

Passing the element OR 7, the signals of the memory blocks 4 and 6 take the form of rectangular pulses (see FIG. 2, i) with a duration

O T g, the period of which is equal to Ti. The DC filter 8 averages the pulse signal. The graph of the output signal of the measuring transducer is shown in

j fig. 2, k.

Thus, in the measuring transducer, the pulses are uniformly distributed before they are averaged by the DC filter. Consequently, the output signal of the converter does not contain a low-frequency component and does not impose significant restrictions on the frequency ratio of the two input signals, which makes it possible to expand the operating frequency range and increase its speed.

Claims (2)

1. Karpov R. G. Technique of pulse-frequency modeling. - M., “Mechanical Engineering, 1969, p. 117-119, Fig.68. 2. Leitman, MB, Melik-Shakhnazarov, A.M. Compensation Measuring Transducers of Electrical Values. M., “Energie, 1978, p. 199-201, FIG. 8-9. T- / byk