SU486379A1 - Program Ring Shift Register - Google Patents

Description

one

The invention relates to the field of impulse technology and can be used in computing technology, automation and measuring equipment for communication systems.

A software ring shift register is known, which contains oscillation generators, the output of which is connected to the shift register bus of the shift register.

The purpose of the invention is to increase the speed of the register.

It is achieved that m & m, that the logic “AND-NOT,” OR-NOT, a frequency divider with a decoder and a self-oscillating multivibrator are entered into the register. The output of the multivibrator is connected to the input of a frequency divider with a decoder, the outputs after the TSNI are connected to the first inputs of the circuits “AND-NOT, the second inputs of which are connected respectively to the outputs of the accelerator with the shift register, starting with the third, and the outputs — with the first inputs of the circuit OR . The remaining inputs of the circuit “OR-NOT are connected to the outputs of the first and second digits of the transducer (Il register), and the output of the circuit“ OR-NOT ”to the input of the first digit of the shift register.

FIG. 1 shows the fuction of a 1-ktsionna scheme of a software ring shift register; in fig. 2 - patterns for wiring.

(The software ring shift register contains triggers 1-10, the AND generator

pulses of this frequency, logic circuit “OR-NOT 12, logic circuits“ AND-NOT 13-20, divider 21 frequencies with a decoder, self-oscillating multivibrator 22.

In operation, the self-oscillating multivibrator 22 generates rectangular pulses with a HIGH frequency (0.1-0.5) Hz, fed to a frequency divider with a decoder (Fig. 2, a). In this case, the signals shown in FIG. 2 are formed at the outputs of the decoder. 2, b, and.

Signal with constant level “1, received from the first output of the decoder

(Fig. 2, i) is applied to the AND-HE 13 logic circuit, the second input of which simultaneously receives a signal from trigger 3, and ensures that the signal from trigger 3 is continuously transmitted to the OR-NO 12 circuit.

This achieves the continuous inclusion of the trigler 3 through the scheme "OR-NOT to the software ring shift register. To the AND 14 circuit, the signal with the level “L” is fed from the second output and the decoder.

(Fig. 2,3).

The absence of a signal with a level of “1 for an interval of time ti - tz causes the absence of a signal at the output of the circuit“ AND-NOT 20 and excludes for a given time interval

trigger 10 from the work of the program many circular .th shift register. Similarly, at the time interval t - / 2, the operation of the flip-flops 9, 10, etc., is terminated.

Thus, the number of triggers in the software ring shift register changes at regular intervals, providing alternate period change (Ring shift register. In this case, the length of time intervals during which the generator produces pulsed groups of a certain density is determined by the period of the multivibrator 22. The frequency of this multivibrator ,, can thus be used to regulate the frequency of the change in the density of pulsed pruop, the wire alternating it with the speed most convenient for the operator. isimo1sti on operator skill and otvetst1ve1nnosti produced by measuring the selected rate can be changed, providing in each case a sufficient duration of a frame on a scale pointer instrument signal urovl corresponding to the set density pulse groups. Assuming the time required for carrying out readings of at streloch1nomu device records readings equal

(2 + 10) seconds, the frequency of the multivibrator is adjustable within (0.1-0.5) Hz.

Subject invention

A software ring shift register containing a pulse generator, the output of which is connected to the shift register shift bus, characterized in that, in order to simplify and increase the speed of the register, it contains AND-NOT, OR-NOT frequency divider and self-oscillating multivibrator, the output of which is connected to the input of a frequency divider with a decyfrater, whose outputs are connected respectively to the first inputs of the circuits "AND-NOT, the second inputs of which are connected respectively to the outputs of bits 1" register, starting with the third, and the outputs to the first inputs of the OR circuit, the remaining inputs of which are connected to the first and second bits of the shift register, and the output of the circuit OR is not connected to the input of the first digit of the shift register.

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