SU467453A1 - Clock Generator - Google Patents

Description

The invention relates to the field of automation and computing tests, in particular to cHHxpOHHSupyiouiH.M devices, and can be used in highly stable L111II communication encoders and in digital computers.

The lime clock generator containing quartz gey | rator, whose outputs and switches to the first inputs of the first and second triggers, respectively, the control circuit, the output of which is connected to the second input of each trigger, and the outputs of the triggers through the combiational logic circuit and connected to the input pulse former.

 In the known generator of clock pulses, the sigals from the output of the humusmator, and, consequently, the clock pulses have irregularities in the neighboring periods, because of the lack of accuracy in the phase shift and the time difference between the trigger triggers.

In order to improve the accuracy of the distribution of clock pulses over time, the outputs of the KBapiteBoro generator are connected to the remaining inputs of a logic circuit, and one of the inputs of the control circuit is connected to the third inputs of each Tpiirrepa.

FIG. 1 shows the functional scheme of the proposed clock generator; pa fng. 2 - Dnagrams

The work of the proposed clock pulse resiepaTOpa.

The proposed generator contains a crystal oscillator 1, a control circuit: n 2, triggers 3 and 4, a combination logic circuit 5, and a driver of i.muls 6.

Works proposed geirator clock pulses as follows.

The signals of the crystal oscillator 1, shifted in phase by 180 °, are fed to the inputs of the installation “1 flip-flops 3 and 4 and the combination logic circuit 5. The inputs of the installation“ 1 flip-flops 3 and 4 are matching circuits. The output "About each trigger 3 n 4 is connected with two schemes of combinational logic circuit 5 and the installation input" 1 of another trigger. These inputs of each trigger 3 n 4 are supplied with a negative signal from control circuit 2. The inputs “O of each trigger 3 and 4” are connected to the “Stop and output” 1 pulse of another trigger.

For convenience, we assume that the circuit elements have positive logic, when "1 corresponds to BbicoKo: iy voltage level, and" O - to low voltage level. The triggers 3 and 4 are set to the initial state of the emulsions "Sgon", and from the output of "About each of them" the "Onions" are removed, the coincidence of which on the input is combined with the logical

Circuit 5 sets at its output "O regardless of what goes on the remaining inputs of this combinational logic circuit 5.

When an impulse is applied. Starting at the output of control circuit 2 produces an enable signal. If it appears in the time interval, then at the output of the "1 trigger 3" phase A resolution signal coincides with the control circuit 2 and the "unit supplied from the zero output of trigger 4. ., a high voltage level is removed from the output of "b". Signals taken from the shoulders of trigger 3 prohibit the match at the input of the installation “1 trigger 4 and forcefully delay this trigger in the initial state at the input of the installation“ O In addition, the signal taken from the output of “On the trigger 4, prohibits the passage of phase B through the combined logic circuit 5 and removes the forced setting“ On at its output.

At time ts 1, independent of when a pulse is received. Running in the time interval ti-tg, positive pulses appear at the output of the combination-logic logic 5, representing phase inversion A, which are converted by frequency and duration in pulse shaper 6. During iodacation of the pulse, the stop trigger 3 is set / returns to its initial state and the formation of the clock pulses is stopped, so from the output of the combinational logic circuit 5 the o.

If the trigger enters the 1z-ti time interval, T | rigger 4, which prohibits the setting (B1 trigger 1, starts from the moment t4, from the output of the combinational logic circuit 5, the pulse driver b is given phase B inversion

When the pulse starts, the iz-u trigger, when the phases overlap, begin: trigger both triggers 3 and 4. Since Tpnrreipbi 3 and 4 are covered by reciprocal feedback through the inputs of the installation o and b then finally only one trigger is set to state “B”, and the other is forcibly returned to state “O.”

FIG. 2, b the case is when trigger 4 is set to state 1, and trigger 3 is returned to the initial state. It can be seen from the diagram that a false signal arises at the output of trigger 3, which does not go to the output of the combinational logic circuit 5, since the vertex of the “And this combinational logic circuit 5” at this moment phases A and B have the value “1 and support in the temporal to-ts at the output of the comM: bi-wide logic circuit 5, the state “O. Starting from the moment of time t of the pulse generator 6, the inversion of phase B begins to arrive.

PREPARATION AND RESULTS

A clock pulse generator containing a crystal oscillator, the outputs of which are connected to the nerve inputs of the first and second triggers, respectively, the control circuit, the output of the controller is connected to the second input of each trigger, and the output of the trngers, through a combinational logic circuit, are connected to the input of the pulse generator, characterized in that in order to increase the accuracy of the clock clock distribution, the outputs of the quartz oscillator are connected to the rest of the inputs of the combinational logic circuit, and one of the inputs with control emy connected to third inputs of each flip-flop.

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