SU1437956A1 - Variable master generator for thyristor inverter - Google Patents

Abstract

The invention relates to electrical engineering and can be used in the control of converters. frequencies. The purpose of the invention is to increase the accuracy of the power control of the inverter. At the start of operation, the trigger 5 is found in a single state. The counting of pulses arriving at the counting input from timer 3 is allowed. After the N-ro pulse of the clock generator 1, a pulse appears at the output of timer 3, which sets the trigger 5 to the zero state. Pulse counting in timer 3 is prohibited, and in timer 4 it is allowed. After the second pulse of the clock generator 2, which enters the input of the timer 4, at its output a pulse is inserted that sets the trigger 5 to the unit state at the input. § This pulse is an output signal. 1 W1.

Description

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with

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The invention relates to a converter technique and can be used in digital control systems of semiconductor frequency converters, in particular inverters.

The aim of the invention is to increase the accuracy of the power control of the inverter. .

The drawing shows the functional diagram of the device.

The device contains the first and second, clock generators 1 and 2, the outputs of which are connected to the counting inputs of the first 3 and second 4 timers, respectively, the outputs of which are connected respectively to the R and S-BXO RS-flip-flop 5, direct and inverse outputs of which are connected to inputs G for recording timers 3 and 4 respectively. In addition, timers 3 and 4 are provided with data inputs D for communication with a data line of a computing device, such as a computer or microprocessor.

The device works as follows.

The data inputs D to timers 3 and 4 add the division factors N, and NJ, calculated in the computing device, from the process program and the current state of the control object, which determine the output frequency of the control object.

With a high signal level (1) at the input of the timer. 1: even the pulses of the clock generator are allowed, with low (O) - prohibited.

Let the period of the following pulses of the clock generator 1 be T, and the clock generator 2 be T + T. At the beginning of operation, trigger 5 is in a single state (high level at the direct output). This means that the counting of pulses arriving at the counting input from timer 3 is allowed, since at its input G a high level signal is given from the direct output of trigger 5.

After the N, th pulse of the clock generator 1, which enters the input C of timer 3, a pulse with a duration appears at the output of the last. - on inverse), This means that from now on it is forbidden with.

0

about

Q g

five

0

pulse counting in timer 3 and enabled in timer 4.

After the pulse of the clock generator 2, which enters the input of the timer 4 with the period T + 5T, a pulse of duration T + S T appears at the output of the latter, again setting the trigger 5 into a single state on the input. This pulse is the output of the device. Thereafter, the processes are repeated.

From the above it can be seen that the period of the following pulses at the output of the device (output, imera 4) is equal to

Yours T N, + (T + T) .N ,,

where ST is the difference between the periods of the first 1 and second 2 clock generators. For normal operation of the device

it is necessary that SE is satisfied

condition

ST T / N ..

Claims (1)

Thus, the device is able to provide high accuracy in controlling the output power of the inverter, since the discreteness of the change in its output frequency is limited when; given T, N and N by the magnitude of the frequency difference of the clock generators. The resolution of the proposed device is much lower than the known ones. Invention Formula A controlled master oscillator for a thyristor inverter comprising a first clock oscillator, the output of which is connected to the counting input of the first programmable timer equipped with data inputs and the counting resolution input, characterized in that, in order to increase the power control accuracy of the inverter, it is equipped with an RS trigger, the second clock generator and the second programmable timer, then the output of the second clock generator is connected to the counting input of the second timer, the outputs of the first and second timers are connected respectively GOVERNMENTAL to R- and S-RS-trigger inputs, the forward and inverted outputs are connected to inputs authorization account the first and second timers, and output controlled oscillator is the output of the second timer.