SU815887A1 - Device for monitoring pulse train - Google Patents

Description

(54) DEVICE FOR CONTROL OF SEQUENCE

PULSES

The first input of the second unit is connected with the clock pulse pulse; the inverse output of the first TpKiiepa is connected to the second input of the second trigger unit and the first input of the third unit trigger, the zero input of which is connected to the forward output of the second trigger, the second input of setting the first trigger to zero is connected to the direct output of the third trigger, the installation input into the unit of the first trigger is connected to the inverse output of the second trigger, the second input of setting the third trigger to unit, connected to the pulse bus of the initial installation, and the input of the installation to zero of the second trigger is connected to the bus controlled pulses.

FIG. 1 shows a structural electrical circuit of the device; in fig. 2 - diagrams, by dream, and his work.

The device contains a trigger 1 control, a trigger 2 controls, trigger 3 memory. Bus 4 — input (installation input into trigger unit 3) for a pulsed initial installation; bus 5 — emergency (installation input at zero trigger 2) for monitored pulses; bus 6 — input (combined inputs to zero setting trigger 1 and installation into a trigger trigger 2) for clock pulses.

The inverse output of trigger 1 is connected to the installation inputs to the unit of flip-flops 2 and 3. The direct output of trigger 2 is connected to the input of the installation to zero of the trigger 3. The inverse output of trigger 2 is connected to the input of the installation to unit trigger 1. The direct output of trigger 3 is connected to the trigger input to the zero trigger 1.

The R-S-triggers used in the device can be built on potential AND-NOT elements.

The device for controlling the pulse train operates as follows.

The device is reset to the initial state by the pulse of the initial installation arriving on the bus 4. Upon receipt, at time to, of the initial setup pulse from bus 4, i.e., a low voltage level, a high voltage level is established at the forward output of trigger 3, at the inverse output of trigger 1, the forward and inverse outputs of trigger 2 are high voltage levels. With the end of the setup pulse (the appearance of a high voltage level on bus 4) at time t. The device is ready for operation.

At time t, a controlled pulse arrives at the bus 5 and a low voltage level is set at the inverse output of the trigger 2. When a clock pulse (coincident with the controlled pulse) arrives on bus 6 at time tj, a low voltage level is established at the inverse output of trigger 1 and, therefore, a high (initial) voltage level is maintained at the forward output of trigger 2.

At the end of the monitored pulse, at time t4, the inverse output of flip-flop 2 sets a high voltage level, and at the end of the clock pulse, at time tg, the inverse output of flip-flop 1 sets a high voltage level. Thus, the trigger 3 of the memory remains in a single healthy state in the presence of a controlled pulse.

In the absence of a controlled pulse (in the time diagram it is conventionally shown by a dotted line) and the receipt of the next clock pulse at the time te, a low voltage level is applied to the forward output of the control trigger 2 at the input to the zero setting of the memory trigger 3. The trigger 3 is switched, and a low voltage level is established at its forward output, indicating the absence of a pulse in a controlled sequence. In addition, a low voltage level from the direct output of memory trigger 3 arrives at the input to setting zero of control trigger 1, confirming its state and preventing its possible switching by successive pulses.

Thus, the arrival of subsequent monitored pulses on bus 5 does not change the state of the malfunction — a low voltage level on the output bus of the device.

The trigger 3 of the memory will be reset to the initial single state only when the initial setup pulse arrives on bus 4 (set to one) before the next monitoring cycle. The previously described cycle of operation is repeated.

Thus, connecting the second input to the zero setting of the first flip-flop to the forward output of the third flip-flop blocks the control trigger, which, together with the introduction of the initial set impulses bus and the monitored impulses bus, ensures the device for controlling the pulse sequence.

Claims (3)

1. Author's certificate of the USSR 337782, cl. G 06 f 11/00. 1972. 2. Authors certificate of the USSR 371691, cl. H 03 K 21/34, 1973. 3. Authors certificate of the USSR 465738, cl. H 03 K 23/02, 1974. 1