SU1190491A1 - Single pulse generator - Google Patents

Abstract

A SINGLE PULSE FORMER containing a first RS-Tuna trigger, a second trigger with a counting input, an inverter, a clock pulse generator, characterized in that, in order to improve speed and simplify the device, a switch is inserted into it, a third trigger with a counting input, the I- element NOT, the R-and S-inputs of the first trigger are connected to the control signal through the switch, the direct output of the first trigger is connected to the combined / -inputs of the second and third triggers, the inverse outputs of the second and third triggers are connected With their information inputs, the direct output of the second trigger and the inverse output of the third trigger are connected respectively to the first and second inputs of the NAND element, and its third input combined with the counting input of the second trigger is connected to the output of the clock NAND is connected to the counting input of the third trigger and through the inverter to the output of the single pulse generator. ; o o 4; o

Description

The invention relates to a pulse technique and can be used in systems for the transmission of discrete messages and in computer equipment.

The purpose of the invention is to increase the speed and simplify a single pulse shaper.

The drawing shows an electrical schematic diagram of the proposed device.

A single pulse shaper contains the first trigger 1 of the RS-thp, the second trigger 2 with the counting input, inverter 3, the 4-clock pulse generator, the switch 5, the third trigger 6, the AND-NE element 7, and the R and S inputs of the first trigger 1 are connected with the control signal bus 8 through the switch 5. The direct output of the first trigger 1 is connected to the combined / -inputs of the second and third triggers 2 and 6, the inverse outputs of the second and third, the triggers 2 and 6 are connected to their information inputs, the direct output of the second trigger 2 and inverse output of the third tr igger 6 is connected to the first and second inputs of the NAND 7 element respectively, and its third input, combined with the counting input of the second, trigger 2, is connected to the generator output 4 clock pulses, the output of the NAND element 7 is connected to the counting input of the third trigger 6 and through the inverter 3 to the output of a single pulse shaper.

The device works as follows.

In the initial position, the control signal from the bus 8 of the control signal in the form of a logical zero is fed through switch 5 to the input of the first trigger 1. The first and third triggers 1 and 6 are in the state "1, and the second trigger 2 in the division mode two frequency generator 4 clock pulses. The output signal is zero.

The control signal in the form of a logical zero is fed through the switch 5 to the / input of the first trigger 1, setting it to the zero state. As a result, by the negative voltage drop from the direct output of the first trigger 1, the second and third triggers 2 and 6 are set to zero

condition. In this case, no pulse is generated at the output of the device for forming a single pulse. In this state, the first trigger 1 is held for another until

the control signal is applied to its zero input, and the duration of this control signal can be arbitrary. The control signal is removed from the input of the first trigger 1 and in the form of a logical "O" is fed to its input, sets it

0 to state "1, while allowing the control of the second and third triggers 2 and 6 on the counting input.

With the arrival of the next pulse of the clock sequence, a sequence of pulses appears at the forward output of the second trigger 2, a frequency two times less than the clock one that goes to one of the inputs of element 7. The second input of this element receives the clock sequence pulses from the output of the generator 4

0 clock pulses. At the inverse output of the third flip-flop 6, a high level is applied to the third input of the EE element 7. As a result of multiplying, a single pulse of the clock sequence of pulses appears in the inverse form, which sets the third flip-flop 6 into the single state with its falling edge. This leads to the fact that the element AND-NOT 7 is locked for the next pulse of the clock sequence of the generator 4 clock pulses. Device

 the formation of single pulses comes to its original state. The generated single pulse from the output of the element AND-HE 7 is fed to the input of the inverter 3, where it is inverted and fed to the output 9 of the device.

In a single pulse shaper, there are no restrictions on the duration of the control signal, since a single pulse at the device output is formed after removing the control signal, and the cycle time of switching off the control signal can be quite small, equal to twice the trigger time 1, t. It depends only on the speed of the integrated circuit. This provides an extension of the range of input signals.

Claims (1)

A SINGLE PULSE SHAPER containing a first trigger / iS-type, a second trigger with a counting input, an inverter, a clock generator, characterized in that, in order to improve performance and simplify the device, a switch, a third trigger with a counting input, an And element are introduced into it -NOTE, moreover, the R- and S-inputs of the first trigger are connected to the control signal bus through the switch, the direct output of the first trigger is connected to the combined /? Inputs of the second and third triggers, the inverse outputs of the second and third triggers are connected to with its information inputs, the direct output of the second trigger and the inverse output of the third trigger are connected respectively to the first and second inputs of the AND-NOT element, and its third input, combined with the counting input of the second trigger, is connected to the output of the clock generator, the output of the AND-NOT element connected to the counting input of the third trigger and through the inverter to the output of the single pulse shaper.