SU1450091A1 - Apparatus for clock synchronization and extraction of pulse train - Google Patents

Abstract

The invention can be used for the number of pulse coding of information, is a shaper of a series of pulses, the number of which in a packet depends on the duration of the input asynchronous signal, performs a temporary tie of the asynchronous signal to the clock frequency pulses. The purpose of the invention is to expand the functionality by ensuring the formation of a controlled pulse train and reducing the criticality to the duration of the input signal is achieved by introducing stop and reset tires 10 and 11 connected respectively to the D input and to the R input of the trigger 1. The device also contains triggers 2 and 3, elements AND 48, input bus 9, 1 PIN 12 clock pulses and output buses 13 and 14. 1 sludge. i SL 4 SP

Description

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The invention relates to a pulse technique, in particular to a series of impulses of a series of pulses, the number of which depends on the duration of an asynchronous signal, performing a temporal reference of an asynchronous signal to a clock frequency, and can be used for number-pulse coirding information. The aim of the invention is to expand the functionality by ensuring the formation of a controlled pulse train and reducing the criticality of the duration of the input signal.

The drawing shows an electrical functional circuit diagram of the device. The device contains the first 1, second 2 and third 3 triggers from the first to the fifth elements AND-NOT 4-8, the input bus 9, the bus 10, the stop bus 11, the bus 12 clock pulses, the first 13 and the second 14 output tires.

The input bus 9 is connected to the S-input DOM of the first trigger 1, whose D input is connected to the stop bus 10, the R input to the reset bus 11, and C to the second output bus 14 and to the output Then the element AND-NOT 8, the first input of which is connected to the output of the second. element AND-NOT 5, with the first input of the third element AND-NOT bis, the first R-input of the third trigger 3, and the second input - with the output of the fourth. AND-NE 7, with the second input of the third element AND-NOT bis first S-in - the house of the third trigger 3. The output of the first trigger 1 is connected to the first one.,. the input of the first element AND-NOT 4, to the second R- and S-inputs of the third trigger 3 and to the S-input of the second trigger 2, the D-input of which is connected to the common bus output bus 13, and the output with the third input of the third element AND-NOT 6, the Second input of the first element AND-NO 4 is connected to the bus 12 clock pulses and to the first input of the fourth element AND-NOT 7, and the output to the first input of the second element AND - NO 5, the second input of which is connected to the inverse output of the third trigger 3, connected by a direct output to the second input of the even erto of NAND 7.

The device works as follows.

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A zero signal arriving on PMne 11 at the R input of the trigger 1, the latter is set to the initial (zero) state and a low potential of its output keeps the trigger 2 in the unit state, and also holds on the forward and inverse outputs of the trigger 3 high potential and element 4 closes at the first input. At element 5 there will be a low potential, which sets a high potential at the output of elements 6 and 8, and inverted clock pulses from the bus 12 are formed at the output of element 7.

The zero signal from bus 9 arrives at the S input of trigger 1 and sets it to one. This opens element 4 and at its output inverted clock pulses are generated from bus 12, which arrive at the first input of element 5. In addition, a low potential and a trigger 3 are removed from the second R and S inputs of trigger 3, depending on the signal , acting on tire 12, is set to one or zero state by a low potential from the output of element 7 or 5, respectively. If, for example, the signal from bus 9 arrived at the moment of the presence of a positive pulse on bus 12, the trigger 3 is set to one by a zero signal from the output of element 7. A low potential from the inverse output of trigger 3. sets a high potential at the output of element 5, which opens elements 6 and 8; Therefore, when a positive pulse is formed at the output of the element 7, corresponding to the pause of clock pulses from the bus 12, negative pulses are formed at the output of elements 6 and 8. A negative pulse from the output of element 6 enters the bus 12 and to the C input of the trigger 2. On the falling front of this pulse, the trigger 2 is set to the zero state and low potential of its output closes the third input element 6. Thus, at the output of element 6 ( on bus 13), a single pulse is always formed. Negative pulses from the output of the element 8 are fed to the bus 14 and to the C input of the trigger 1. After the termination of the signal on the bus 9, in the absence of a signal on the bus 10

trigger 1 returns to the zero state on the trailing edge of the negative pulse from the output of element 8 and the low potential from its output sets trigger 2 to one, closes element 4 on the first input and holds high potential on the forward and inverse outputs 3 . the device is in the initial state and waits for the next signal to arrive on bus 9

Thus, the signal from the bus 9, the device generates negative pulses corresponding to the pulse or pause between the pulses of the clock frequency, 13 and 14.

Moreover, a single pulse is formed on bus 13, and a train of pulses corresponding to the duration of the signal on bus 9 is formed on bus 14.

If a high potential is applied to the bus 10, then the signal from the bus 9 causes the formation of high impulses. However, in this case, the trigger 1 returns to its initial state after the signal is removed from the bus 10, i.e. on the bus 14, a forcing of a controlled pulse train occurs, corresponding to the time from the supply of the control signal to the removal of the signal from the bus 10,

Claims (1)

The invention of the device is a clock synchronizing and wiring pulses containing the first trigger, the output of which is connected to the first input of the first NAND element, the second input of which is co0 five 5 o 0 five 0 one with the bus. tactic pulses, the output with the first input of the second element AND-NOT, the output of which is connected to the first input of the third element AND-NOT, the output of which is connected to the first input bus and the C input of the second trigger, whose D input is connected with a common bus, direct output - with the second input of the third NAND element, the third trigger, the direct output of which is connected to the first input of the fourth NAND element, the fifth NAND element, the input and second output tires, that in order to enhance functionality by providing neither the formation of a controlled series of pulses and a reduction in the criticality to the duration of the input signal, the stop and reset buses are introduced into it, which are connected respectively to the D-BXO house and to the R input of the first trigger, the C input of which is connected to the second output bus and with the output of the first IS element whose first input is connected to the first R input of the third trigger and the second IS output of the second input, whose second input is connected to the inverse output of the third trigger, the first S input of which is connected to the third input the third element is NOT with the second input of the first NAND element and with the output of the fourth NAND element, the second input of which is connected to the second input of the first AND-NO element, the first input of which is connected to the second R- and S-inputs of the third trigger and the S-input of the second trigger