SU1383473A1 - Pulse train-to-square pulse converter - Google Patents

Abstract

The invention relates to a pulse technique and can be used in pulse signal processing systems. The invention makes it possible to expand the functionality of a pulse train that is achieved by converting input batches with a varying period of pulse traces from batch to batch. The converter contains input bus 1, delay element 2, differentiating -chain 3, elements 4, 5 and 6, triggers 7, 8, 9 and 10, element 11 BAN, pulse counter 12, pulse generator 13, buffer register 14, shift register 15, multiplexer 16 and output bus 17. Elements And 5 and 6, pulse generator 13, triggers 8, 9 and 10, pulse counter 12, buffer register 14, shift register 15 and multiplexer 16 with the corresponding connections are entered, In accordance with the present invention, a delay control block, providing an expansion of the functions national device capabilities. 2 Il. . (L

Description

P

00

00

oo

four;:

WITH

The invention relates to a pulse technique and can be used in systems for processing pulse signals.

The purpose of the invention is to expand the functionality by allowing the input series to be converted with a varying period of the pulse from series to series.

FIG. 1 is an electrical functional diagram of the device} in FIG. 2 - time diagrams | we, which explain his work.

 A pulse train I to a rectangular pulse contains. . I input bus 1, delay element 2, I differentiating circuit 3, three elements ITA 4-6, four trigger 7-10, prohibition element 11, pulse counter 12, pulse generator 13, buffer register 14, shift register 15, multiplexer 16 and the output bus 17, and the input bus 1 is connected to the first input of the element And 5 and through the delay element 2 to the first inputs of the element 1 BAN 11 and the element 4, the second input of which is connected to the second input of the ban 11 and the output of the differentiating circuit 3, and the output is from: 5-input of the trigger 7, the R-input of which is connected to the output of the element ZAPR T 11, and the output with the output bus 17 and the C input of the trigger 10, the R input of which is connected to its direct output and the R inputs of the counter 12, the buffer register 14, and trigger 9, the C input of which is connected to the the output of the trigger 8 and the first input element And 6, and the inverse output with the second input element And 5, the output of which is connected to the C input of the trigger 8, the inverse output of which is connected to the C input of the buffer register 14, the information inputs of which are connected to the corresponding the outputs of the counter are 12 pulses, and the outputs - with the corresponding: emaciated control inputs the multiplexer 16, the output of which is connected to the input of the differentiating circuit 3, the zero information input is connected to the zero bus, and the remaining information inputs to the corresponding outputs of the shift register 15, the C input of which is connected to the output of the pulse generator 13 and the second input of the And 6 element, output

which is connected to the C-input of the counter 12 pulses.

Elements 5 and 6, a pulse generator 13, triggers 8-10, a pulse counter 12, a buffer register 14, a shift register 15 and a multiplexer 16 with corresponding connections constitute a delay control block.

Q The converter works as follows.

In the initial state, the trigger 7 and the block are time delayed are in the zero state. A series of pulses arriving at the input bus 1 of the device (Fig. 2a), after a time t ,, determined by the delay in the delay element 2, arrives at the input of the And 4 element and at the D input of the shift control unit 15 of the delay control unit

(Fig.26). In addition, the input pulse train is fed to the input element AND 5 of the delay control block. A series of pulses coming from the output of the delay element 2 (Fig. 26) is delayed in the delay control unit for a time tj and fed to the input of the differentiating circuit 3 (Fig. 2b) at the output of which short pulses are formed, coinciding in time with the leading edges delayed pulses of the series (Figg).

The delay time in the delay control block must be such that the condition

five

T.CH t, + g,,

0

t.

five

where TC is the period of the pulse following in the series; and bu - pulse duration

series.

This condition is ensured by v because the delay control block measures the time interval between the first and second pulses of the input series and saves its value in a digital code until the end

input pulse train.

I

In this case, the output element f. And 4 all short pulses of a series pass from the output of differentiating circuit 3, except for the last one, corresponding to the last pulse in the series (Figure 2d). The first pulse with the output t of the element AND 4 switches the trigger 7 to one state (Fig. 2g). The last pulse from the output of the differentiating circuit 3 passes to the output of the prohibition element 11 (Fig. 2e) and, when it enters the second input of the trigger 7, resets the latter to the zero state (Fig; 2g).

The operation of the delay control block consists in determining the pulse repetition period of the input series and the delay of a series of pulses coming from the output of the delay element 2 to the input of the block element AND 5 for the period and proceeds as follows,

The R initial state of the direct outputs of the triggers 8–10 is zero logic, counter 12 and buffer register 14 are zeroed.

The first impulse of the input series (Fig. 2a), arriving at the input of the element AND 5, on the other input of which a single logical level arrives from the inverse output of the trigger 9, causes the appearance of a single logical level at the output of the element 5 and raises the first trigger 8, a single logical level from the direct output of which permits the passage of pulses from the output of the master oscillator 13 through the element 6 to the counting input of the counter 12 pulses.

The second impulse of the input series (Fig. 2a) passes through the element I 5 and, with its front, resets the trigger 8 to the initial state, thereby increasing the period of the following impulses of the input series. The cut of the pulse coming from the direct output of the trigger 8 to the input of the trigger 9 coaxes it. The zero logic level from its inverse output blocks element AND 5. The pulses of the master oscillator 13, which passed through the element 6, are recorded in counter 12. Thus, the period of the pulse train is converted into a binary code that is on the front of the pulse from the inverse output of the trigger 8 is written to the buffer register 14. The outputs of the buffer register 14 are connected to the control inputs of the multiplexer 16, the input code of which controls the connection of the corresponding information input of the multiplexer 16 to its output, which is output delay control block.

The D-input of the shift register 15 receives a series of pulses delayed with respect to the input delay in element 2 by the time t,. The shift of the pulses arriving at the D input of the shift register 15 is carried out

pulses of the oscillator 13. When the pulse, shifting in the register 15, reaches the output connected to that input of the multiplexer 16, which is connected to its output in accordance with the input control code, a single level pulse appears at the output of the delay control unit, the duration which is equal to the duration of the pulse arriving at the input bus 1 of the device.

Since the operation of the period-to-binary control code and the shift of the input pulses in the shift register 15 occur in parallel with time, the conditions must be met

0 5

0

five

0

five

0

zg

4,6t, 2T

Tz. 48+ t, g + t ,, + t ,,, + t ,,,

where ty is the delay time of element 2

delays; Tj - the period of the pulse

generator 13} tjg - switching delay time

element and 5; switching delay time

trigger 8; switching delay time

element and 6j switching delay time

counter 12;

 the switching delay of the buffer register 14, the switching delay of the multiplexer 16. Thus, each pulse from the output of the delay element 2 is delayed for a period at the output of the delay control block.

The delay control unit returns to its initial state via a slice of the output rectangular impulse coming from the output bus 16 of the device to the C input of the trigger 10. The trigger 10 is energized and immediately reset, since its direct output is connected to its R- input, forming a short unit impulse that returns trigger 9, x counter 12 and buffer register 14 to the initial state.

Thus, the proposed device allows converting a series of pulses with a different pulse period to rectangular pulses, since the parameters of the device do not depend on the pulse period of the input series.

Claims (1)

Formula 6 Shade Array A pulse train to a rectangular pulse containing an input bus connected to the input of the delay element, an element whose output is connected to the S input of the trigger, a first input to the output of the differentiating circuit and a first input of the BAN element, and a second input to the second input the BANCH element, the output of which is connected to the R input of the trigger, the code of which is connected to the output bus, so that, in order to enhance the functionality by ensuring the possibility of transforming the input series with varying By a pulse following period, a delay control block is inserted in it, containing the first and second elements AND, the first, second and third triggers, a pulse counter, a shift register, a buffer register, a clock generator and a multiplexer whose output is the code of the control unit delays and is connected to the input of the differentiating circuit, the information inputs of the multiplexer, except for zero, are connected to the corresponding outputs of the shift register, the zero information input is with a common length, and the control inputs are with current outputs of the buffer register, the C input of which is connected to the inverse output of the first trigger, information inputs with the corresponding outputs, the pulse counter, and the R input with the R input of the pulse counter, R inputs of the second and third triggers, and direct output. the third trigger, the C input of which is the first input of the controllable delay unit and connected to the output bus, the D input of the shift register, which is the second input of the controllable delay block, is connected to the output of the delay element and the second input of the And element, and C- entrance - with you the pulse generator and the first input of the first element And, the output of which is connected to the C-input of the pulse counter, and the second input - with the direct output of the first trigger and C-input of the second trigger, the inverse output of which is connected to the first input of the second element And, the second input which, being the third input of the controllable delay unit, is connected to the travel bus, and the output is connected to the C-input of the first trigger.