SU1200401A1 - Device for time separation of pulse signals - Google Patents

Abstract

A DEVICE FOR TIME DIVIDEING PULSE SIGNALS, containing four triggers, two NAND elements, the first and second input buses, which are connected to the counting inputs of the first and second triggers, respectively, the forward outputs of which are connected to the information inputs of the third and fourth triggers, respectively, Wee outputs of which are connected to the first inputs of the first and second elements NAND, respectively, the outputs of which are connected to the inputs of the installation in the zero state of the first and second triggers, respectively, clock bus, which is connected to the second input of the second NAND element, and two output buses, characterized in that, in order to expand the functionality of the device, two NO elements are inserted into it, and the clock bus is connected to the input of the first element whose output is connected to the counting input of the fourth trigger, to the second input of the first NAND element and to the input of the second NO element, the output of which is connected to the counting input of the third trigger, the inverse output of which is connected to S with the input and into the zero state of the fourth flip-flop, the inverse (L output of which is connected to the setup input to the zero state of the third flip-flop, the inverse outputs of the first and second triggers are connected to the information inputs of the corresponding triggers, and the forward outputs of the third and fourth triggers are connected to the first and second output tires, respectively. J o:

Description

The invention relates to a pulse technique and can be used to separate in time two pulse signals.

The purpose of the invention is the expansion of the functional capabilities of the device due to the possibility of forming time-separated impulse signals, for a duration equal to both the duration and | i, the period of the clock pulses;

H4 of FIG. 1 npeflCTaBJieHa functional device circuit design for temporal separation of pulsed signals; in fig; 2 - time diagrams that show his work.

The device for temporarily separating the pulse signals contains four triggers 1-4, two elements AND-NOT 5 and 6, two elements NOT 7 and 8, first and second input buses 9 and 10, which are connected to the counting inputs of the first and second triggers 1 and 2 respectively, the direct outputs of which are connected to the information inputs of the third and fourth triggers 3 and 4, respectively, the direct outputs of which are connected to the first inputs of the first and second elements AND-NOT 5 and 6, respectively, the outputs of which are connected to the inputs of the zero state of the first and in flip-flops 1 and 2, respectively, and a bus 11 clock pulses, which is connected to the second input of the second element AND-NOT bis the input of the first element NOT 7, the output of which is connected to the counting input of the fourth trigger 4, with the second input of the first element AND-HE 5 and with the input of the second element HE 8, the output of which is connected to the counting input of the third trigger 3, the inverse output of which is connected to the installation input to the zero state of the fourth trigger 4, the inverse output of which is connected to the installation input to the zero state of the third trigger 3, the inverse outputs of the first and second triggers 1 and 2 are connected to the information inputs of the corresponding triggers 1 and 2, and the direct outputs of the third and fourth triggers 3 and 4 are connected to the first and second output buses 12 and 13, respectively.

The device for temporal separation of pulse signals operates in the following manner.

In the initial state, on the input buses 9 and 10, on the direct outputs of the triggers 1-4 there is a low voltage level (level, and on the outputs of the AND-NE elements 5 and 6 there is a high voltage level (level I), on the bus 11 clock pulses arrive (Fig. 2).

When a signal arrives at the input bus 9 (Fig. 2fli), the trigger 1 trans. switches off at time ti (Fig. 2), and at time t, on the clock edge (Fig. 2) switches to one state and flip-flop 3 (Fig. 2), the output pulse arrives on bus 12.

At the same time, the low level signal on the inverse output of the trigger 3 triggers 4 is held in the O state. From the beginning of the clock pulse pause (ti) on the bus 11 (Fig. 2B), the AND-HE element 5 (Fig. 2e) activates the trigger 1 in the initial zero state (Fig. 22), but the trigger 4 does not switch (Fig. 2i), since it is blocked by the R-level O from the inverse output of the trigger 3.

At the moment of time t /, the second input pulse (Fig. 2S) posts the input bus 10 and switches the flip-flop 2 to the unit state (Fig. 2a). At time tc, the trigger 3 is switched to the initial state, the formation of the output pulse on the bus 12 ends (Fig. 2). At time t. from the beginning of the clock pause, the signal from the output of the element HE 7 and the signal from the direct upstream of the trigger 2 trigger 4 switches to a single state (Fig. 2c), and a pulse is produced on the output bus 13, and in the output O from the inverse output trigger 4 is held in the zero state trigger 3 (Fig. 25). At time t on the front of the clock pulse on the bus 11 is turned off element AND NOT 6 / Fig. 2) and sets to its original state

trigger 2. At time tj from the start of the clock pause, the signal from the HE element 7, trigger 4 is set to the initial zero state, the formation of the output pulse on bus 13 ends.

With simultaneous arrival of pulses through the input buses 9 and 10 (t.), They switch to one state.

triggers 1, and 2 (fig.), and

In time the moment t on the pulse front from the output of the element NOT 7, the trigger 4 is switched to one state, a pulse is output to the output bus 13 (Fig. 2h), and the level O from the inverse output of trigger 4 causes the trigger 3 to be held in the state O (Fig .2

At time t., On the clock edge, an AND-NE 6 element is opened (Fig. 2g) and the trigger 2 is set to the initial zero state (Fig. 2). At the moment of time t .. from the beginning of the pause on the pulse from the output of the element HE 7, the trigger 4 is set to the initial state (Fig. 2 and).

At the time point C, on the front of the clock pulse from the output of the element HE 8, the trigger 3 switches to one state, a pulse is output to the output bus 12 (Fig. 2j). At the time point C, it triggers the element. AND-NO 5 FIG. 2ft) and switches the trigger 1 to the initial zero state of FIG. 22, and on the front of the next clock pulse from the output of the element HE 8 at time t, x the trigger 3 returns to the initial state (Fig. 25).

The third possible variation of input pulses is shown in FIG. 2. The operation of the device does not differ from the previously discussed options. When forming a pulse on one output bus, it is envisaged to prohibit the formation of a signal on the other output bus.

The pulses on the output tires 12 and 13 are formed with a standard duration equal to the period of the clock pulse. If necessary, the output signals can be removed from the elements AND-NOT 10 and 11. The duration of these signals is equal to half the period of the following (duration) clock pulses.

Triggers 1 and 2 are used in

counting mode, i.e. their inputs D are connected to inverse outputs. A constant level 1 can be connected to the inputs D of these flip-flops, since in both cases recording 1 to triggers 1 and 2 is carried out along the leading edges of the signals at inputs C with logical I at inputs D, and the reset by inputs R to zero the state does not depend on the signals at the inputs C and D (when using triggers in the OT mode, logical 1, inputs D are received from the inverse outputs of these triggers, and when using triggers in the register mode, from a constant level logical 1)

t, is tf tf

Claims (1)

DEVICE FOR TIME SEPARATION OF PULSE SIGNALS, containing four triggers, two NAND elements, first and second input buses, which are connected to the counting inputs of the first and second triggers, respectively, whose direct outputs are connected to the information inputs of the third and fourth triggers, respectively, whose direct outputs are connected to the first inputs of the first and second elements AND NOT, respectively, the outputs of which are connected to the inputs of the installation in the zero state of the first and second triggers, respectively, the bus so new pulses, which is connected to the second input of the second AND-NOT element, and two output buses, which is characterized by the fact that, in order to expand the functionality of the device, two NOT elements are introduced into it, while the clock bus connected to the input of the first element NOT, the output of which is connected to the counting input of the fourth trigger, to the second input of the first element AND, and to the input of the second element NOT, the output of which is connected to the counting input of the third trigger, whose inverse output is connected q to the input to zero with the state of the fourth trigger, the inverse output of which is connected to the zero state of the third trigger, the inverse outputs of the first and second triggers are connected to the information inputs of the corresponding triggers, and the direct outputs of the third and fourth triggers are connected to the first and second output buses, respectively. 1 1200 401 ²