SU1539978A1 - Device for time division of pulsed signals - Google Patents

Abstract

The invention relates to a pulse technique and can be used in devices for generating, issuing and processing information. The purpose of the invention is to expand the functionality. The device contains triggers 1 and 2, element I3, key 7 with memorization of the control signal, bus 8 clock pulses, input buses 9 and 12, output buses 13 and 14. Introduction of element I4, elements EXCLUSIVE OR 5 and 6, bus 10 logical units and control bus 11 provides the device the ability to change the priorities of service input signals, i.e. changing the order of occurrence of pulses on output tires 13, 14, while they appear simultaneously on tires 9, 12, depending on the logic level on bus 11. 2 Il.

Description

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The invention relates to a pulse technique and can be used in devices for generating, issuing and processing information.

The aim of the invention is to enhance the functionality by making it possible to change the service priorities of the input signals.

FIG. 1 shows a functional diagram of the proposed device; in fig. 2 - time diagrams that show his work.

The device contains the first 1 and second 2 triggers, the first 3 and second 4 elements, the first 5 and second 6 elements EXCLUSIVE OR, the key 7 with the control signal memorization, the bus 8 clock pulses, the first input

bus 9, bus 10 logical units, bus 11 control, the second input bus 12, the first 13 and the second 14 output tires.

Clock inputs of triggers 1 and 2 are connected respectively to input buses 9 and 12, and their information inputs are connected to bus 10. The reset input is triggered, gera 1 is connected to bus 13 and the first output of key 7, whose information input is connected to bus 8, the second the output is connected to the bus 14 and the reset input of trigger 2, the inverse and direct control inputs are connected respectively to the outputs of the EXCLUSIVE OR 5 and 6j elements whose first inputs are connected to the output of the AND 4 element. The second input of the EXCLUSIVE OR element 5 is connected to the first input of the element

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4 and the forward output of the trigger 1, the inverse output of which is connected to the first input of the element 3, the output is expensively connected to the second input of the element EXCLUSIVE OR 6, the second input is connected to the forward output of the trigger 2 and the second input of the element 4, the third input of which is connected to the ine 11.JQ

The device for temporal separation of pulse signals works as follows.

After turning on the device, bus 10 should be set to jj 1, and bus 11 should have a logical level that determines the priorities for serving the input signals for the case

their simultaneous arrival on the input tires 9 and 12, i.e. the JQ ordering of output signals on buses 13 and 14. In this device, the input signal on the input bus 9 is set to correspond to the output signal generated on bus 25 13, and the input signal on bus 12 corresponds to the output signal generated on bus 14.

In the initial state, the triggers 1 and 2 are set to O, as a result, at the outputs of the elements 3 and 4 and at the outputs of the elements EXCLUSIVE OR 5 and 6 there are levels O. Since there are also O levels at both control inputs 7, then in accordance with the rule of operation of the key with memorization of the control signal, the clock pulses coming from the bus 8 to the information input of the key 7 are

its exits and its tires 13 and 14 are not long

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FIG. 2 shows signals at the following points of the functional diagram: on bus 9 (a), on bus 12 (b), on bus 8 (c), on bus 11 (d), on direct, (e) and inverse (e) the trigger outputs i, the forward trigger output 2 (g), the output element And 4 (g), the output element And 3 (i), the outputs of the elements EXCLUSIVE OR 6 and 5 (respectively k, l), on the bus 13 (m) on the bus 14 (n).

Consider the operation of the device at level O on the bus 11.,

If input pulses arrive

on buses 9 and 12 at the same time, then triggers 1 and 2 are simultaneously set to 1. As a result, the forward control input key 7

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the O level continues to operate, and its intrusive control input is set to level 1. The first clock pulse arriving at bus 8 after switching over flip-flops 1 and 2, in accordance with the current combination of control signals, passes to the first output of switch 7 and goes to bus 13 and trigger reset input 1. As a result, on the bus

13 an output pulse is formed, and the trigger 1 is set to O, which ensures the formation of an EXCLUSIVE OR 5 element at the output and an inverse control input of the key 7 of the level O. Level 1, formed at the inverse output of trigger 1, arrives at the first input of the And 3 element and forms output level 1, which goes through the EXCLUSIVE OR 6 element to the direct control input of the key 7. In accordance with the levels 1 and О operating respectively on the forward and inverse control inputs of the key 7, the second clock pulse passes from the bus 8 to Torah output key 7 and supplied to the bus

14 and trigger reset input. As a result, an output impulse is formed on bus 14, trigger 2 is set to 1, blows into O, and the device returns to its original state.

Thus, while the input pulses are simultaneously received on buses 9 and 12 and if there is a level O on bus 11, the device generates two time-separated pulses on buses 13 and 14, and the pulse on bus 13 is formed first. This indicates that mode, a higher priority service has an input signal to the bus 9.

If the input pulse arrives at bus 9, then trigger 1 switches to 1. As a result, level O continues to act on the forward control input of key 7, and level 1 is set at its inverse control input. The first clock pulse arriving at bus 8 after switching the trigger 1, in accordance with the current combination of control signals, passes to the first output of the key 7 and is fed to the bus 13 and the reset input of the trigger 1. At the same time, an output pulse is formed on the bus 13, the trigger 1 is set to

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Oh, and the device returns to its original state.

Thus, when the input pulse arrives on the bus 9 and if there is a level O on the bus 11, the device generates a pulse on the bus 13, and on the bus 14 the level O

If the input pulse arrives on bus 12, then trigger 2 switches to 1. As a result, level 1 is sequentially formed at the output of the AND 3 element, at the output of the EXCLUSIVE OR 6 element and the forward control input of the key 7, at the inverse control input of which continues to be stored. level O. The first clock pulse arriving at bus 8 after switching over trigger 2, in accordance with the current combination of control signals, passes to the second output of key 7 and enters bus 14 and the reset input of trigger 2. At the same time, bus 14 is formed with the output pulse, the trigger 2 is set to ON, and the device returns to its original state.

Thus, when an input pulse arrives on the bus 12 and if there is a level O on bus 11, the device generates a pulse on bus 14, and level O remains on bus 13

Consider the operation of the device at level 1 on the bus 11.

If the input pulses are fed to buses 9 and 12 simultaneously, then the triggers 1 and 2 are simultaneously set to 1. As a result, the output of the element And 3 continues to act on the level O, and the output of the element And 4 forms the level 1, which acts on the first inputs of the elements EXCLUSIVE OR 5 and 6. This ensures the installation of a level 7 key 1 on the forward control input and storing the level O control on its inverse input. The first clock pulse arriving on bus 8 after switching triggers 1 and 2, in accordance with the current combination the control signal passes to the second output of the key 7 and is fed to the bus 14 and the reset input of the trigger 2. At the same time, an output pulse is formed on the bus 14, and the trigger 2 is set to O, which leads to the formation of the output element And level 4 O. This provides installation3H786

KU on the direct and inverse inputs of the control key 7, respectively, levels O and 1. The second clock pulse passes from bus 8 to the first output of key 7 and is fed to bus 13 and the reset input of trigger 1. As a result, bus 13 produces an output pulse , trigger 1 is set to JQ is cast to O, and the device returns to its original state.

Thus, with the simultaneous arrival of input pulses on buses 9 and 12 and in the presence of level 1 on

J5, bus 11, the device generates two time-separated impulses on buses 13 and 14, with the pulse generated on bus 14 first. This indicates that in this mode, a higher service priority has an input signal to bus 12.

If the input pulse arrives on bus 9, then trigger 1 switches

25 in 1. As a result, at the outputs of the AND 3 and 4 elements, at the output of the EXCLUSIVE OR 6 element and at the direct control input of the key 7, the O level continues to be maintained, and at the output

The element EXCLUSIVE OR 5 and the inverse control input of switch 7 is set to level 1. The first clock pulse arriving on bus 8 after switching trigger 1, in accordance with the current combination of control signals, passes to the first output of key 7 and goes to bus 13 and input reset trigger 1. At the same time on the bus 13 is formed the output

pulse trigger 1 is set

to O, and the device returns to its original state.

Thus, when an input pulse arrives on the bus 9 and if there is a level 1 on the bus 11, the device generates a pulse on the bus 13, and on the bus 14 the level O remains.

If the input pulse arrives on bus 12, then trigger 2 switches to 1. As a result, level 1 is sequentially formed at the output of the FROM element, at the output of the EXCLUSIVE OR 6 element and on the forward control input of the key 7, which continues to remain at the inverted control input level O. The first clock pulse arriving at bus 8 after switching trigger 2, in accordance with the current combination of control signals, passes to the second output of key 7 and goes to bus 14 and the reset input of trigger 2. At the same time, pin 14 forms the output pulse, trigger 2 is set to O, and the device returns to its original state. Thus, when an input pulse arrives on the bus 12 and if there is a level t on bus 11, the device generates a pulse on bus 14, and level O is stored on bus 13.

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the invention

A device for temporarily separating pulse signals containing the first element I, the first and second inputs of which are connected respectively to the inverse output of the first trigger and to the forward output of the second trigger, clock inputs of which are connected respectively to the first and second input buses, the reset input of the first trigger connected to the first output bus and the first exit key

After turning on the device, the state is $ with memorization of the control signal,

neither triggers 1 and 2 can differ from zero ones. However, this does not lead to a loss of device performance, since always after a finite time interval in accordance with the described operation algorithms the triggers 1 and 2 will be reset to the initial state under the action of the output pulses of the device.

Thus, after turning on the device, its initial setting is carried out autonomously at a finite interval of time, not exceeding in the worst case three periods of clock pulses on the bus 8. This always allows to take into account the device uptime for use when using it in a specific hardware.

The application of the invention allows to expand the functionality of the device, i.e. provides the ability to change the priority of service input signals. This increases its practical value and contributes to its wider use in electronic equipment.

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the information input of which is connected to the clock pulse bus; the sec output is connected to the second output bus and the reset input of the second trigger 20 characterized by the fact that, in order to expand the functional capabilities due to the possibility of changing the priorities of servicing the input signals, the second element AND , the first and second elements EXCLUSIVE OR, the control module and the logic unit bus, which is connected to the information inputs of the first and second triggers, whose direct outputs are connected respectively the first and second inputs of the second element I, the third input of which is connected to the control bus, and the output connected to the first inputs of the first and second elements EXCLUSIVE OR, the second inputs of which are connected respectively to the direct output of the first trigger and the output of the first element AND, and the outputs are connected respectively to the inverse and direct control inputs with a key that stores the control signal.

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the information input of which is connected to the clock pulse bus; the second output is connected to the second output bus and the reset input of the second trigger, 0 characterized in that, in order to expand the functionality by providing the possibility of changing the service priorities of the input signals, the second element I was entered into it, The first and second elements are EXCLUSIVE OR, the control bus and the bus of a logical unit that is connected to the information inputs of the first and second triggers whose forward outputs are connected to the corresponding The first and second inputs of the second element are And, the third input of which is connected to the control bus, and the output is connected to the first inputs of the first and second elements EXCLUSIVE OR, the second inputs of which are connected respectively to the forward output of the first trigger and the output of the first element And, and the outputs connected, respectively, to the inverse and forward control inputs of the key with the storage of the control signal.

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Claims (1)

Claim A device for temporary separation of pulse signals containing the first element And, the first and second inputs of which are connected respectively to the inverse output of the first trigger and to the direct output of the second IQ trigger, the clock inputs of which are connected respectively to the first and second input buses, the reset input of the first trigger is connected to the first output bus and the first output of the key with the memory of the control signal, the information input of which is connected to the clock bus, the second output is connected to the second output bus and input the reset of the second trigger, 20 characterized in that, in order to expand the functionality by providing the ability to change the priorities of servicing the input signals, 25 the second AND element, the first and second EXCLUSIVE OR elements, the control bus and the logical unit bus that is connected to the information inputs of the first and second trig3Q gerov ^ direct outputs of which are connected respectively to the first and second inputs of the second element And, the third input of which is connected to the control bus, and the output is connected the first inputs of the first and second elements ³⁵ comrade XOR, the second inputs of which are connected respectively to the direct output of the first flip-flop and the output of the first AND gate and the outputs 4Q respectively connected to the direct and inverse inputs key management latched control signal. in figure 1 1 -------- 1 n _______ n _____________ n ______ ......P t f — I P ... __P___ t R ~ 1 P P P t η P t GT GT n n ... ί ........- P_  ,.-P-------------- __ΓΊ_ t