RU1811003C - Device for separating pulses - Google Patents

Abstract

Usage: the invention relates to automation and computer engineering and can be used in devices for supplying pulses arriving via several independent channels. The device contains: inputs (1, 2, 3), triggers (4, 5, 6), delay elements (7, 8, 9), AND elements

Description

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The invention relates to automation and computer engineering and can be used in devices for supplying pulses arriving via several independent channels.

The purpose of the invention is to increase reliability by simplifying the device and expanding the scope.

The drawing shows an electrical functional diagram of the device.

The device contains inputs 1-3 of the device, triggers 4-6, delay elements 7-9, elements AND 10-14, element OR 15, clock input 16, one-shot 17, device output 18.

The inputs 1-3 of the device are respectively connected to the C-inputs of the triggers 4-6, the direct outputs of which are respectively connected to the first inputs of the AND 10-12 elements, the direct output of the trigger 4 is also connected to the first input of the OR element 15, the output of the one-shot 17 is connected to the device output 18, with the second input of the element And 10 and the first inputs of the elements And 13-14, the outputs of the elements And 10-14 are respectively connected to the inputs of the delay elements 7-9, the outputs of which are respectively connected to the R-inputs of the triggers 4-6, the outputs of the elements And 11, 12 are respectively connected to volts the second and third inputs of the OR element 15, the output of which is connected to the enable input of the one-shot 17, the signal input of which is connected to the pulse synchronization input 16, the inverse output of the trigger 4 is connected to the second inputs of the elements 11-12, the inverse output of the trigger 5 is connected to the third input of the element And 12, the inverse output of the trigger 7 is connected to the fourth input of the element And 12, the D-inputs of the triggers 5-8 are connected to the logical bus 1.

The device can be implemented, for example, on microcircuits of the 155, 555 series.

The device operates as follows.

Before pulses arrive at inputs 1–3, triggers 4–6 are in the initial state; at the direct outputs of these triggers, zero signal levels are present. The operation of the device is enough to consider the example of a three-channel option.

When a pulse arrives at any of the input buses of the device, for example, bus 1 of FIG. 1, the corresponding trigger transitions to a single state.

Since, after the trigger transition, the single state at the input of the OR circuit is logical 1, which from the output of the OR circuit 15 goes to the first

the input of the one-shot 17 and upon receipt of a clock pulse from the input of the device 16 to the second input of the single-shot 17, a pulse of a given duration is generated at its output, which is fed to the output of the device 18 and to the input of the And 10 element through the delay line 7 to the input of the R-trigger 4, resetting it in the initial state.

When pulses arrive simultaneously at two inputs of the device, for example 2 and 3, the triggers 5 and 6 are set to a single state, while the signal from the inverse output of the trigger 5 of the channel with a lower number closes the And 12 element

5 other channel. Since the resolving signal levels are present at all inputs of the AND element 11 of the channel with a lower number, a signal appears at its output, which acts through the OR element 15

0 input 1 of the one-shot 17 and in the presence of a clock pulse at the second input of the single-shot 17, a pulse arriving at the output of the device 18, and through the element And 13 and the delay element 8 to R

5 input trigger reset 5, which leads to the return of the elements of the channel .2 with a lower number to its original state and the removal of the ban from the input of the element And 12 channel 3, the operation of which is similar to the second

0 channels.

When a pulse arrives at all three inputs of the device at the same time, all input triggers are set to a single state. In this case, the signal from the inverse

5 of the trigger output 4 closes the elements And 11, 12 of the second and third channels, and the signal from the inverse output of the trigger 5 closes the element And 12 of the third channel. At all the inputs of the element And 10 of the first channel, resolving potentials appear. Therefore, the first channel fulfills the impact on the input pulse, as described above.

After returning to the initial state of 5 elements included in the first channel of the device, resolving potentials appear at all inputs of the element And 11 of the second channel. Elements of the second channel process the impact of the input signal

0 is similar to the first channel. After the elements of the second channel return to their initial state, the resolving potentials appear at all inputs of the element And 12 of the third channel, after which the third output pulse of the device is generated in the third channel. Thus, in this case, the output 18 of the device will generate three pulses that are issued synchronously. With pulses arriving at the synchronization input 16 .. If pulses are not simultaneously received at the inputs of the device (pulse repetition period of the pulse repetition period), the operation of each channel separately does not varies.

When pulses arrive at the device inputs, when the pulse repetition period of the synchronization pulse repetition period, the channel with the lower number is the first to process the input action, as discussed above.

Thus, the device, regardless of the position of the input signals, sequentially generates pulses in each channel and outputs the device synchronously with the pulses received at the synchronization input 16. If the synchronization input 16 is applied to the pulses, and the potential is logical 1, then at the device output 18 pulses will appear as pulses arrive at the inputs of the device, 1, 2, 3. The minimum pulse repetition interval at the device output 18 is determined by delay elements 7, 8.9.

Thus, the introduction of the pulse synchronization input 16 made it possible to expand the field of application of the device, and the introduction of two elements And 13, 14, logical 1 bus and communications made it possible to simplify the circuit, increase its reliability by eliminating two pulse shapers from the known device and reducing the number of element inputs AND.

Claims (1)

The claims Pulse separation device. containing a trigger in each channel, delay element and AND element, first input which is connected to the direct output of the trigger of its own channel, the inverse trigger output of each 1st channel is connected to the inputs of elements And from (I + 1} th through p-1 channels, the output of the delay element in each channel is connected to the reset input of the trigger of this channel, the counting input of which is connected to the input bus of this channel, a single-shot, OR element, characterized in that, in order to increase reliability by simplifying and expanding the scope of application, (n - 1) And elements are introduced into it, the first input of each of which , starting from the first, is connected respectively to the output of the AND element of the m-ro channel (where m 2, 3,.,., p) and the corresponding input of the OR element, the first input of which is connected to the direct output of the trigger of the first channel, the second inputs (p - 1) of the AND elements are connected to the output of the one-shot, the first and second whose inputs are connected respectively to the input of the clock pulses and the output of the OR element, the output of the And element of the first channel is connected to the input of the delay element of this channel, the output of each j-ro element And (where j 1, 2 ... (n - 1) is connected respectively to the input delay element of the m-th channel, the output of the device is connected to the output of a single-shot, the D-inputs of the trigger of the n channels are connected to the bus of the logical unit.