SU839034A1 - Pulse shaper - Google Patents

Description

(54) PULSE FORMER

Claims (2)

The invention relates to a pulse technique, in particular to a pulse shaper with a predetermined delay, and can be used in devices of computer technology and automation. A device containing two triggers and an inverter producing an output signal with a predetermined delay when the control signal is longer than a predetermined value is known. The disadvantage of this device is its complexity. The closest technical solution to the present invention is an interference suppression device, containing two triggers, each of which has single inputs, zero and separate synchronization in O, and direct and inverse outputs, and a separate installation in O of the first trigger is The control input of the device, the synchronization input of the first trigger, the input, and the direct output of the second trigger, the output of the device, the direct output of the first trigger, are connected to the single input of the second trigger, whose output is inverse Inonii with a single trigger input hepBoro 2. The disadvantage of this device is the low noise immunity caused by the fact that at short propadenii control signal to the inputs of a separate installation. both triggers receive a zero signal, forcing the triggers to zero, with the result that a false zero signal is generated at the device output. Recovery of the output signal is possible after 1-2 periods of the clock frequency. The aim of the invention is to improve noise immunity. The goal is achieved by the fact that a pulse driver containing two triggers, the synchronization input of the first trigger is connected to the clock pulse bus, the installation input to O is connected to the control pulse bus, the forward output is connected to the single input of the second trigger, the inverse output of which is connected to a single the input of the first trigger, and the direct output to the output of the driver, an inverter and a third trigger are introduced, the direct output of which is connected to the zero input of the second trigger, the synchronization input and the zero input of the third trigger The inputs to the sync inputs of the first and second triggers, the single input of the third trigger are connected to the direct output of the second trigger, and the installation input to O via an inverter with the installation input to the first trigger. The use of an additional three-meter and inverter ensures that the device reliably forms an output signal with a given delay due to the short-term loss of the control signal at the device input. FIG. Figure 1 shows the principle of the electrical circuit of the pulse former; in fig. 2 - time diagrams of his work. The device contains triggers 1-3 and inverter 4, and the triggers have 5-8, respectively, single, synchronization, zero, separate outputs, outputs 9 and 10 of matching directly and inverse, bus of 11-stroke pulses, bus G2 of control pulses and output bus 13 of the driver . The pulse shaper operates as follows. In the initial state on bus 12 there is a zero signal (Fig. 26 which goes to input 8 of trigger 1, forcibly sets a zero signal on its output 9. When a clock pulse arrives from bus 11 (Fig. 2a) to inputs b of triggers 2 and 3, zero signals are set at their outputs 9. When a single control signal arrives on the bus, trigger 1 is enabled, and a zero signal from the output of inverter 4 through input 8 blocks the operation of the trigger .3, which is forcibly held in the zero state. front of the first one The output pulse received on bus 11 at output 9 of trigger 1 sets a single signal (Fig. 2c), which is fed to input 5 of trigger 2. On the back front of the next clock pulse, trigger 2 is thrown to one state, and trigger 1 - in zero, at output 9 of trigger 2 and on output bus 13, a single signal is set (Fig. 2d), inputted to input 5 of trigger 3, and at course 10 of trigger 2, a zero signal inputted to input 5 of trigger 1. At the same time, clock pulses arriving at inputs b of triggers 1 and 3, confirm zero values They are not triggered, the zero signals from outputs 9 of which by inputs 5 and 7 prohibit triggering with 2 clocks. On the output bus 13, a single signal is maintained until the control signal is removed. After removing the control signal on bus 12 and at input 8 of trigger 1, a zero signal is set, which forcibly keeps trigger 1 in the zero state and through inverter 4 removes blocking of trigger 3 at input 8. On the trailing edge of the first clock pulse that came after removing the control signal, at output 9 of trigger 3, a single signal is set (Fig. 2d), which is fed to input 7 of trigger 2 and prepares the transfer of trigger 2 to the zero state. On the trailing edge of the next clock pulse at the outputs 9 of the flip-flops 2 and 3, zero signals are set, prohibiting the flip-flop of these flip-flops by the clock pulses at inputs 7 and 5, respectively. The feed back to the initial state. At the same time, the duration of the control pulse t ,, p ((xy. 26) must satisfy the condition, p 7 / T. The delay of the output signal at the beginning (end) of the control pulse (- Zaa.k.) is equal to (1-2 ) T (Fig. 2d). If a single control pulses with a duration tvnp T (Fig. 26) arrive at the shaper in the initial state, then on the falling edge of the first incoming clock pulse, trigger 1 is thrown into the single state, and the flip-flop of trigger 2 to a single state can occur on the trailing edge of the second clock pulse only when one the second signal at input 5 of trigger 2. If a zero signal appears on bus 12 before the clock pulse arrives, then output 9 of trigger 1 is set to a zero signal, which prevents the trigger 2 from switching over to unit state on a clock pulse. The former remains in its original state If in the driver during the formation of a single signal on bus 12 there occurs a short-term disappearance of a single signal by time T, then on the falling edge of the first incoming clock pulse trigger 3 is thrown into a single state However, a flip-flop triggered 2 to the zero state can occur on the trailing edge of the second clock pulse only with a single signal at input 7 of trigger 2. If a single signal is restored on the bus 12 before the arrival of the second clock pulse, then at output 9 of trigger 3 it is set to zero , a signal that prohibits the flip of the trigger 2 to the zero state on a clock pulse. On the output bus 13, a single signal is stored. Thus, if the control signal at the input momentarily disappears, the output signal does not change. The use of the proposed Shaper in computing devices and automation allows improving the reliability and accuracy of devices. The invention of the pulse shaper, which contains two triggers, the synchronization input of the first trigger is connected to the clock pulse bus, the setup input is connected to the control pulse bus, the forward output is connected to the single input of the second trigger, the inverse output of which is connected to the single input of the first trigger, and My output to the driver output, characterized in that, in order to improve the noise immunity, an inverter and a third trigger, the direct output of which is connected by the null input of the second trigger, are entered into it, the synchronization input and the zero input of the third flip-flop is connected to the synchronization inputs of the first and second flip-flops, the single input of the third flip-flop is connected to the direct output of the second flip-flop, and the installation input to O via an inverter with the installation input to the first flip-flop. Sources of information taken into account in the examination 1. UK Patent 1299420, cl. H 3 R, 1972. 2. Authors certificate of the USSR 519857, cl. H 03 K 5/153, 1974 (prototype).