SU945968A1 - Single pulse shaper - Google Patents

Description

one

The invention relates to a pulse technique and can be used to temporarily couple signals in automation devices and you, digital technology, exchanging information at an asynchronous rate.

A device for synchronizing pulses is known, which contains three triggers: a ger, two NAND elements and an NOT element. It reliably generates output pulses if the length of the pause between adjacent input signals is greater than the period of the clock frequency pulses D.

However, if the duration of the pause between the two input signals is less than the period of the clock frequency pulses and coincides with the pause of the clock pulses, the device will not be able to generate output pulses on the falling edge of the first input signal, it will receive two input signals in one.

The closest technical solution is a single pulse shaper containing input and output triggers, a reset trigger, three AND-NOT 2 elements}.

This driver allows to receive single pulses from the leading edge of the input signal of any duration with reference to the clock frequency of the device, however, its stable operation is possible only if the pause between the input asynchronous signals is longer than the period of the clock synchronizing pulses.

15 If the duration of the pause will be. less and coincides in time with a pause between the pulse frequency and the clock, then the known device will not be able to form the output of the synchronized pulse along the leading edge. the second input signal, i.e. the device does not respond to the end of one and the beginning of another input

signal, and will take both input signals for one. This is due to the fact that when there is a pause between the input signals, the input trigger will not return to the initial zero state, because the signal of a logical unit arrives at its zero input. This reduces the reliability of the driver.

The purpose of the invention is to increase the reliability of the device.

The goal is achieved by the NTO in the single pulse shaper containing the first trigger, the second trigger whose single input is connected to the output of the first trigger and the first input of the first NAND element, the second input of which is connected to the first input of the second NAND element, the third input The first element AND-NOT is connected to the unit output of the second trigger, and the output of the first element AND-NOT is connected to the unit input of the third trigger and the first input of the third element AND-NOT, the second input of which is connected to the unit output third first trigger, the third input of the third element IS-Not connected to the output of the second element AND-Not and connected to the zero input of the third trigger, and the output of the third AND IS NOT connected to the zero input of the second trigger, zero output of which is connected to the second input of the second element AND-NOT, the elements NOT i are added to it. the NAND element, the first input of which is connected to the single input of the first trigger and with the output of the NO element, the second input of the additional NAND element is connected to the zero output of the second trigger, and the output is connected to the zero input of the first trigger.

Figure 1 presents the functional diagram of the generator single pulses; Fig. 2 shows timing diagrams explaining the operation of the former.

The shaper of single pulses contains the element NOT 1, the triggers 2,3 and k, the elements AND-NOT 5-8, the bus 9 of the input signal, the bus 10 synchronized pulses, the output bus 1 1.

The shaper works as follows.

The absence of an input signal on the bus 9 of the device (Fig. 26) allows the clock pulses to pass through the bus 1

Claims (2)

(Fig. 2 a / through the elements AND-NE 6 and 7 of FIGS. 2 and, 2 e) install the triggers 2 (Fig. 2 d) and 4 (Fig. 2 k to the zero state, as a result of which the output signal is low trigger 2 translates trigger 3 (FIG. 2e) into a single state and simultaneously prohibits the passage of a high-order signal from a single output of trigger 3 through the AND-NOT element 5. A low signal level at the output of trigger 4 prohibits the formation of output pulses at the output of the I- element NOT 7. The high level of the input signal arriving at the bus 9 through the element NOT 1 (FIG. 2c sets the toigger 2 into one state and resolving the passage of a signal from a single output of a trigger 3 through an element AND-NE 5 in the presence of a high level of pulses of a clock frequency at its second input. In this case, the output of element AND-HE 5 (FIG. 2) The LOGO-zero signal translates the trigger 4 (Fig. 2k) into a single state and simultaneously prohibits the passage of a high level signal from its output through the AND-HE element 6 (Fig. 2 l). NOT 5 low level clock pulse at the output of the element AND-NOT .7 (figure 2 l) is formed by It drove a low level that goes to bus 11 (FIG. 2 liters of the device, and also triggers the trigger 3 (Fig. 2 g) to the zero state. The low level of the signal from the single output of trigger 3 prohibits the repeated operation of the NAND element 5, and a high level at the zero output of the trigger 3 prepares the activation of the elements NAND 6 and 8 after the formation of the output pulse. The occurrence on the bus 10 of a high clock frequency level provides the formation of a reset pulse at the output of the NAND element 6, which brings the trigger 4 to the zero state. Therefore, the low level of the signal at its output forms the leading edge of the output pulse and prohibits the repeated operation of the element NAND 7 (Fig. 2 l). The high level of the signal at the second input of the element IS-HE 8 (Fig. 2d), coming from the zero output three | - Hera 3, allows the formation of a pulse along the falling edge of the input signal to set the input trigger 2 to its initial state. As a result, trigger 3 (Fig. 2e) is set to one. A high level from its single output allows the formation of an output pulse when the next input signal arrives on the bus 9 of the device. The former is in its initial state and is ready to form a new output pulse. The proposed shaper, as well as the known one, allows receiving single pulses from the leading edge of the input signal of any duration with reference to the clock frequency of the device. In addition, it has a significant advantage, as it ensures reliable operation at any pause length between adjacent input signals due to the lack of criticality to the pause duration of synchronizing pulses .. This was possible due to the formation of a reset pulse for setting to the initial zero state of the trigger 2 immediately on the trailing edge of the input signal (after the output edge of the output signal is output, impulse), which is carried out by the NAND element 8. Such formation of an impulse for setting the trigger Gera 2, in its initial state, makes the operation of the device uncritical to the parameters of the clock frequency pulses, i.e. improve the reliability of work tel. Invention A single pulse shaper comprising a first trigger, a second s три flip-flop, the single input of which s is connected to the output of the first trigger and the first input of the first AND-NO element, the second input of which is connected to the first input of the second AND-NOT element, the third input of the first AND element -NOT connected to a single output of the second trigger, and the output of the first element AND-NOT connected to a single. the input of the third trigger and the first input of the third NAND element, the second input of which is connected to the single output of the third trigger, the third input of the third NAND element is connected to the output of the second NAND element and to the zero input of the third trigger, and the output of the third I element It is NOT connected to the zero input of the second trigger, the zero output of which is connected to the second input of the second NAND element, characterized in that. that, in order to improve the reliability of the device, the elements NOT and the NAND element are additionally introduced in it, the first input of which is connected to the single input of the first trigger and the j output of the NO element, the second input of the additional AND element NOT connected to the zero output of the second tri1- Hera, and the output is connected to the zero input of the first trigger. Sources of information taken into account in the examination 1. The author's certificate of the USSR 680160, cl. H 03 K 5/13, 1978. 2. USSR Author's Certificate for Application No. 2853 9b / 18-21, cl. H 03 K 5/13, 1979.. KZU x: "5j I one "SI g D1 WITH J I j