SU1411950A1 - Pulse shaper - Google Patents

Abstract

The invention relates to a pulse technique and can be used in devices for processing pulse signals. The purpose of the invention is to reduce the recovery time due to the introduction of two elements OR 4 and 5 in the driver and the second and third output buses 11 and 12 and the element AND-NOT 6. In addition, the driver contains D-flip-flops 1-3, an inverter, the control bus 8, the 9-clock bus, the first output bus Y. The former generates single pulses on the output buses, synchronized with the clock frequency, and indicates the moment of arrival of the action. The introduction of the NAND element and the inverter, as well as the proposed functional connections between the circuit elements, allows using three D-triggers (instead of five in the prototype) and reducing the recovery time. 2 Il. tC (L

Description

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The invention relates to a pulse technique and can be used in pulse signal processing devices.

The purpose of the invention is to reduce the recovery time of the former.

FIG. 1 shows an electrical functional diagram of the former; in fig. 2 - time diagrams that show his work.

The pulse shaper contains the first 1, second 2 and third 3 D-flip-flops, the first 4 and second 5 elements AND, the element NE-6, the inverter 7, the control bus 8, the bus 9 clock pulses, the first 10, the second 11 and the third 12 output buses, with the bus 9 clock pulses connected to the C inputs of flip-flops 2 and 3, the first input of the NAND element 6 and the first input of the OR 5 element, the second input of which is connected to the inverse output of the trigger 2, and the output from R trigger trigger input

2, the D input of which is connected to the D-BXO– trigger house 3 and the output of the trigger 1, | and the direct code to the output bus 12 and the first input of the OR element 4, the second input of which is connected to the potential bus 11, the right the output of the trigger 3 and the second input of the element AND-NOT 6, and the output with the output bus 10 and through the inverter 7 with the R-input and D-input of the trigger 1, the C-input of which is connected to the control bus 8, the output of the element AND NOT 6 is connected to the K-input of the trigger 3. Trigger 2 is triggered on the front, and 1 Trigger 3 - on the decline of the signal from the bus 9 clock pulses,

The pulse shaper operates as follows

In the initial state, the triggers 1–3 are reset. The clock input 9 enters the 1T clock pulses.

In the case of arrival, the input 8 (Fig. 2a) at the time of the presence of a clock frequency pulse on bus 9 (fig. 26) triggers 1 and on the trailing edge of the clock pulse b triggers 3 (fig. 2e) 3 through the element OR 4 (FIG. 2e) And the inverter 7 resets the trigger 1 and holds it in the reset from the stop (FIG. 2c), On the leading edge of the next clock pulse through i, the AND-HE 6 reset the trigger

3, that through the element KII 4 and inverter 7 removes the reset signal from trigger 1.

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As a result, the output of the trigger 3 generates a pulse synchronously with the first after a pause of clock pulses,

In the event of an impact on the bus 8 at the time of the pause of the clock frequency, trigger 1 is activated and trigger 2 is activated on the leading edge of the clock pulse (Fig. 2). The level of logical units; from the output of flip-flop 2 through the WL 4 element and the inverter 7 resets the flip-flop 1. At the trailing edge of the clock pulse, flip-flop 2 is flushed through the OR 5 element.

Thus, the proposed shaper generates single impulses synchronized with a clock frequency at the output tires, indicating the moment of arrival (pulse or pause of the clock frequency). The driver has a speed of no less than half a cycle of clock pulses. It is also not critical to the duration of the input action, and is ready to receive the next pulse on bus 8 immediately after the end of the output pulse.

Claims (1)

The introduction of the NAND element and the inverter, as well as the indicated links, made it possible to significantly simplify the driver (three D-flip-flops instead of five in the known one) and reduce the recovery time. Formula A pulse driver containing an inverter, a first output bus, a control bus connected to the C-pin of the first trigger, the output of which is connected to the D-inputs of the second and third trigger, a clock bus connected to the C-pin of the second trigger, characterized in that , in order to reduce the recovery time of the former, two OR elements are introduced into it, the second and third output buses and the NAND element, the output of which is connected to the K input of the third trigger. Pa. The first input - with the output of the third trigger, the second output bus and the first input of the first element OR, and the second input - with the bus of clock pulses, C-input of the third trigger and the first input of the second OR element, the second input of which is connected to the inverse output of the second trigger, and the output. to the R input of the second trigger, the direct output of which is connected 1D1195P4 with the third output bus and the second input of the first element of the IPD, the output of which is connected to the first output bus and through an inverter with the D input of the first trigger. JlJlJlJglJтnJггL Compiled by S. Ermakov Editor N. Bobkova Tehred L. Serdyukova Corrector, Kravtsova Order 3672/55 Circulation 928 VPIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 P FIG. 2 Subscription