SU1190485A1 - Generator of pulses with respect to leading and trailing edges of input signal - Google Patents

Abstract

FORMER OF PULSES ON THE FRONT AND BACK FRONT OF THE INPUT SIGNAL, containing four flip-flops, inverter, input bus and clock bus, which is connected to the first inputs of the first and second triggers, the output of the second trigger is connected to the first input of the third trigger, the output of the chrome, the output of the outlet, the output of the chrome, the output of the trigger, the output of the trigger, the output of the triggers, the output of the first and second triggers. , the second input of which is connected to the output of the first trigger, characterized in that, in order to increase reliability, the first and second AND-NOT elements are introduced into it, the first inputs of which are connected to by the moves of the third and fourth triggers, respectively, the second input of the first element IS NOT directly, and the second input of the second element IS NOT through the inverter connected to the input bus, the output of the first trigger connected to the second input of the third trigger, and NOT connected to the second inputs, respectively, of the second and first triggers.

Description

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The invention relates to a pulse technique and can be used in automation and computing devices.

The purpose of the invention is to increase reliability.

The drawing shows the electrical circuit of the pulse former along the leading and trailing edges of the input pulses.

The pulse shaper contains four triggers 1-4, inverter 5, input bus 6, bus 7 clock, which is connected to the first inputs of the first 1 and second 2 triggers, the output of the second 2 flip-flops is connected to the first input of the third trigger 3, the output of which is connected to the first input the fourth trigger 4, the second input of which is connected to the output of the first trigger 1, the first 8 and second 9 elements AND-NOT, the first inputs of which are connected to the outputs of the third third and fourth 4 trigger, respectively, the second input of the first element AND-NOT 8 directly and the second input of the second element AND-HE 9 is connected via an inverter 5 to the input bus, the output of the first 1 trigger is connected to the second input of the third 3 trigger, and the outputs of the first 8 and second 9 AND-NOT elements are connected to the second inputs of the second 2 and first 1 triggers.

The device works in the following way.

In the initial state on the bus 7 there are clock signals that go to the single inputs of the flip-flops 1 and 2. On the bus 6 of the input pulses there is a zero potential that goes to the first input of the AND-NE element 8 and the input of the inverter 5, from the output of which the unit potential flows at the first input of the element AND-NOT 9. From the output of the elements AND-NOT 8 and 9, the unit potentials arrive at the zero inputs of the flip-flops 2 and 1. The single potential from the output of the flip-flop 2 goes to the zero input of the flip-flop 3. The single potential from the output of the flip-flop 1 goes to

single inputs of flip-flops 3 and 4. From the output of flip-flop 3, a single potential arrives at the second input of the AND-NE element 8 and the zero input of the trigger 4, from the output of which the zero potential flows to the second input of the AND-HE element 9.

When the rising edge of the input signal appears on the bus 6, a zero potential is formed at the output of the AND-HE element 8. When the next sync pulse appears on bus 7 at the output of flip-flop 2 and output bus 10, a zero-polarity pulse appears, which sets a zero potential at the output of flip-flop 3, which in turn sets a single potential at the output of flip-flop 4 AND-NO 8 unit potential. The subsequent sync signals from the bus 7 to the output bus 10 do not pass, which is ensured by the zero potential from the output of the trigger 3.

0 Thus, on the output bus 10, a pulse is formed corresponding to the leading edge of the input pulse on the bus 6.

At the end of the input pulse on bus 6 (which corresponds to the appearance of the rear

 of the front) at the output of the NANDI element 9, a zero potential is formed, which allows triggering of the trigger 1 on the first clock pulse. In this case, at the output of trigger 1, an impulse appears, which returns the driver to the initial state. Thus, on the output bus 11, a pulse is formed corresponding to the trailing edge of the input signal.

The use of additional NAND elements and new connections in the shaper makes it possible to increase the noise immunity from the effect of various types of noise on the input. In this case, noise immunity increases with increasing ratio, where Tn is the duration of the pause between adjacent clock pulses (the time during which the driver is resistant to interference); T is the duration of the sync pulse.

Claims (1)

PULSE FORMER FOR THE FRONT AND REAR FRONTS OF THE INPUT SIGNAL, containing four triggers, an inverter, an input bus and a clock bus, which is connected to the first inputs of the first and second triggers, the output of the second trigger is connected to the first input of the third trigger input the fourth trigger, the second input of which is connected to the output of the first trigger, characterized in that, in order to increase reliability, the first and second AND-NOT elements are introduced into it, the first inputs of which are connected to the outputs respectively, of the third and fourth triggers, the second input of the first AND-NOT element is directly connected, and the second input of the second AND-NOT element through an inverter is connected to the input bus, the output of the first trigger connected to the second input of the third trigger, and the outputs of the first and second elements AND connected to the second inputs of the second and first triggers, respectively. SU,. „1190485>